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GM71CS17400CJ-5 PDF预览

GM71CS17400CJ-5

更新时间: 2024-10-28 14:51:15
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器
页数 文件大小 规格书
10页 97K
描述
DRAM

GM71CS17400CJ-5 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Base Number Matches:1

GM71CS17400CJ-5 数据手册

 浏览型号GM71CS17400CJ-5的Datasheet PDF文件第4页浏览型号GM71CS17400CJ-5的Datasheet PDF文件第5页浏览型号GM71CS17400CJ-5的Datasheet PDF文件第6页浏览型号GM71CS17400CJ-5的Datasheet PDF文件第7页浏览型号GM71CS17400CJ-5的Datasheet PDF文件第8页浏览型号GM71CS17400CJ-5的Datasheet PDF文件第10页 
GM71C(S)17400C/CL  
18.  
19.  
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying  
data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high  
impedance); if tOEH < tCWL, invalid data will be out at each I/O.  
The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the  
4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-before-  
RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O  
(I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data  
output pin is a high state during test mode read cycle, then the device has passed. If they are not  
equal, data output pin is a low state, then the device has failed. Refresh during test mode  
operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test  
mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh  
cycle or RAS-only refresh cycle.  
In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the  
specified value. These parameters should be specified in test mode cycles by adding the above  
value to the specified value in this data sheet.  
20.  
Rev 0.1 / Apr’01  

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