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GD80960JF33 PDF预览

GD80960JF33

更新时间: 2024-01-05 12:35:04
品牌 Logo 应用领域
英特尔 - INTEL 时钟外围集成电路
页数 文件大小 规格书
90页 1261K
描述
RISC Microprocessor, 32-Bit, 33MHz, CMOS, PBGA196, PLASTIC, BGA-196

GD80960JF33 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA, BGA196(UNSPEC)针数:196
Reach Compliance Code:unknownECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.77
地址总线宽度:32位大小:32
边界扫描:YES最大时钟频率:33.3 MHz
外部数据总线宽度:32格式:FIXED POINT
集成缓存:YESJESD-30 代码:S-PBGA-B196
低功率模式:YES端子数量:196
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA196(UNSPEC)封装形状:SQUARE
封装形式:GRID ARRAY电源:3.3,3.3/5 V
认证状态:Not Qualified速度:33 MHz
子类别:Microprocessors最大压摆率:320 mA
最大供电电压:3.45 V最小供电电压:3.15 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS端子形式:BALL
端子位置:BOTTOMuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

GD80960JF33 数据手册

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Contents  
42 Boundary-Scan Register—Bit Order ..........................................................................................81  
43 Natural Boundaries for Load and Store Accesses......................................................................81  
44 Summary of Byte Load and Store Accesses ..............................................................................82  
45 Summary of Short Word Load and Store Accesses...................................................................82  
46 Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)..................................................83  
Revision History  
Date  
Revision  
Description  
To address the fact that many of the package prefix variables have  
changed, all package prefix variables in this document are now  
indicated with an "x".  
August 2004  
006  
Removed reference to A80960JF-16 from Table 3 on page 15.  
Removed reference to NG80960JC-40, NG80960JC-33, NG80960JS-16,  
and NG80960JF-16 from Table 4 on page 15.  
Removed reference to GD80960JC-40, GD80960JC-33, and 80960JS-16  
in Table 6 on page 16.  
September 2002  
005  
Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and  
80960JF-16 in Table 18 on page 35.  
Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and  
80960JF-16 from Table 21 on page 39.  
Removed reference to 80960JC-40, 80960JC-33, 80960JS-16 and  
80960JF-16 from Table 22 on page 42.  
Added new extended temp device offerings. See Table 5 on page 16.  
Removed PGA package availability from JS/JC/JT processors.  
September 1999  
June 1999  
004  
003  
Changed AC timing parameter TOV1 (min) for extended temp devices only.  
See Table 22 on page 42.  
Merged the 80960JS/JC datasheet information into this datasheet  
(previously named 80960JA/JF/JD/JT 3.3 V Embedded 32-Bit  
Microprocessor datasheet).  
Updated ICC values for the 80960JS/JC/JT processors. Increased  
TIH1 specificationfor the 80960JS/JC/JT processors. Updated  
MPBGA thermal specifications.  
Corrected orientation of MPBGA package diagrams (Figure 6 on page 30  
and Figure 7 on page 31).  
December 1998  
002  
001  
Added Figure 11 on page 46, Figure 12 on page 46, Figure 14 on page 47,  
and Figure 15 on page 48 to distinguish 80960JT 3.3-V and 5-V signal  
derating curves from the 80960JA/JF/JD derating curves.  
This datasheet supersedes revisions to the following 80960Jx datasheets:  
#273109 (JT), #272971-002 (JD), and #276146-001 (JA/JF). In addition to  
combining the documents into one, the following content was changed:  
Figure 1 on page 7: Added MPBGA package to diagram.  
March 1998  
Section 3.2.4, “80960Jx 196-Ball MPBGA Pinout” on page 30: Added new  
Figures 6 and 7, Tables 10, 11 and 13.  
Figure 16 on page 48: Added with the note that follows the figure.  
6
Datasheet  

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