Datasheet > GAL26CV12

GAL26CV12

更新时间： 2024-11-09 22:20:19

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
17页	256K
描述
High Performance E2CMOS PLD Generic Array Logic

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GAL26CV12 数据手册

GAL26CV12

High Performance E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 142.8 MHz

I/CLK

INPUT

I/O/Q

RESET

— 4.5ns Maximum from Clock Input to Data Output

OLMC

— TTL Compatible 16 mA Outputs

— UltraMOS^®Advanced CMOS Technology

I/O/Q

• ACTIVE PULL-UPS ON ALL PINS

• LOW POWER CMOS

— 90 mA Typical Icc

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• TWELVE OUTPUT LOGIC MACROCELLS

— Uses Standard 22V10 Macrocells

— Maximum Flexibility for Complex Logic Designs

• PRELOAD AND POWER-ON RESET OF REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

PRESET

Description

The GAL26CV12, at 7.5 ns maximum propagation delay time,

combines a high performance CMOS process with Electrically

Erasable (E²) floating gate technology to provide the highest

performance 28-pin PLD available on the market. E²technology

offers high speed (<100ms) erase times, providing the ability to

reprogram or reconfigure the device quickly and efficiently.

Pin Configuration

DIP

I/CLK

PLCC

I/O/Q

Expanding upon the industry standard 22V10 architecture, the

GAL26CV12 eliminates the learning curve typically associated with

using a new device architecture. The generic architecture provides

maximum design flexibility by allowing the Output Logic Macrocell

(OLMC) to be configured by the user. The GAL26CV12 OLMC is

fully compatible with the OLMC in standard bipolar and CMOS

22V10 devices.

I/O/Q

GND

I/O/Q

GAL

26CV12

I/O/Q

GND

I/O/Q

Vcc

VCC

GAL26CV12

Top View

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers100% field programmability and functionality

of all GAL products. In addition, 100 erase/write cycles and data

retention in excess of 20 years are specified.

15 I/O/Q

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

June 2000

26cv12_03

12 3 4 5 6 7...17

中文翻译

下载PDF

与GAL26CV12相关器件

型号	品牌	获取价格	描述	数据表
GAL26CV12-15LJ	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
GAL26CV12-15LJB	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
GAL26CV12-15LJIB	LATTICE	获取价格	EE PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28
GAL26CV12-15LP	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PDIP28, PLASTIC, DIP-28
GAL26CV12-15LPB	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PDIP28, SKINNY, PLASTIC, DIP-28
GAL26CV12-15LPI	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PDIP28, SKINNY, PLASTIC, DIP-28
GAL26CV12-15LPIB	LATTICE	获取价格	EE PLD, 15ns, CMOS, PDIP28, SKINNY, PLASTIC, DIP-28
GAL26CV12-20LD/883	ETC	获取价格	ASIC
GAL26CV12-20LD/883C	LATTICE	获取价格	EE PLD, 20ns, PAL-Type, CMOS, CDIP28, CERDIP-28
GAL26CV12-20LJ	LATTICE	获取价格	EE PLD, 20ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28

与GAL26CV12相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

24
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

24
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

50
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

40

产品中心

服务支持

精选活动

关于我们

帮助中心

GAL26CV12

GAL26CV12 数据手册

与GAL26CV12相关器件

与GAL26CV12相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GAL26CV12

GAL26CV12 数据手册

与GAL26CV12相关器件

与GAL26CV12相关文章

您还可以找

您在本页遇到什么问题？