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FX619L2 PDF预览

FX619L2

更新时间： 2024-11-17 22:48:55
品牌 Logo 应用领域
CMLMICRO 半导体
页数 文件大小 规格书
11页 135K
描述
CML Semiconductor Products PRODUCT INFORMATION

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中文翻译

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FX619L2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCJ, LDCC24,.44SQ针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.83压伸定律：CVSD
滤波器：YESJESD-30 代码：S-PQCC-J24
JESD-609代码：e2长度：10.02 mm
功能数量：1端子数量：24
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC24,.44SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified座面最大高度：3.7 mm
子类别：Other Telecom ICs最大压摆率：0.0045 mA
标称供电电压：5 V表面贴装：YES
技术：CMOS电信集成电路类型：CVSD CODEC
温度等级：INDUSTRIAL端子面层：TIN SILVER
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：10.02 mm

FX619L2 数据手册

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CML Semiconductor Products  
PRODUCT INFORMATION  
FX619 'Eurocom' Delta Codec  
Publication D/619/6 September 1997  
Features/Applications  
On-Chip Input and Output Filters  
Designed to Meet Eurocom D1-IA8f  
Meets Stanag 4209 and  
Stanag 4380  
Military Communications  
Delta MUX, Switch and Phone  
Applications  
Programmable Sampling Clocks  
3 or 4-bit Compand Algorithm  
Forced Idle Facility  
Powersave Facility  
Single 5V CMOS Process  
Single Chip Full Duplex Codec  
Full Duplex CVSD* Codec  
DATA ENABLE  
ENCODER FORCE IDLE  
ENCODER INPUT  
MOD  
VDD  
VSS  
ENCODER OUTPUT  
f1  
f 2  
XTAL/CLOCK  
f 0  
XTAL  
CLOCK RATE  
ENCODER DATA CLOCK  
DECODER DATA CLOCK  
VBIAS  
GENERATORS  
FX619  
MODE 1  
CLOCK MODE  
LOGIC  
MODE 2  
SAMPLING RATE  
CONTROL  
ALGORITHM  
3 or 4-BIT  
POWERSAVE  
f 3  
f 1  
DECODER INPUT  
DEMOD  
DECODER OUTPUT  
DECODER FORCE IDLE  
Fig.1 Internal Block Diagram  
Brief Description  
The FX619 is an LSI circuit designed as a  
The encoder has an enable function for use in  
*Continuously Variable Slope Delta Codec and multiplexer applications. Encoder and Decoder  
is intended for use in military communications  
systems.  
Designed to meet Eurocom D1-IA8 with  
forced idle facilities are provided forcing a  
10101010..... pattern in encode and a VDD/2  
bias in decode. The companding circuits may  
external components, the device is suitable for be operated with a 3 or 4-bit algorithm which is  
applications in military Delta Multiplexers,  
switches and phones.  
externally selected. The device may be put in  
the standby mode by selection of the  
Encoder input and decoder output filters are  
powersave facility. A reference 1.024MHz  
incorporated on-chip. Sampling clock rates can oscillator uses an external clock or Xtal.  
be programmed to 16, 32 or 64 k bits/second  
from an internal clock generator or may be  
externally applied in the range 8 to 64 k bits/  
The FX619 is a low-power, 5 volt CMOS  
device and is available in 22-pin cerdip DIL,  
24-lead/pin plastic and 28-lead ceramic  
second. Sampling clock frequencies are output leadless SMT packages.  
for the synchronization of external circuits.  
6.1  
1234567...11

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