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FX614D4-LF-TR PDF预览

FX614D4-LF-TR

更新时间: 2024-01-11 04:41:30
品牌 Logo 应用领域
CMLMICRO 电信光电二极管电信集成电路
页数 文件大小 规格书
17页 329K
描述
Modem, 1.2kbps Data, CMOS, PDSO16, LEAD FREE, SOIC-16

FX614D4-LF-TR 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LEAD FREE, SOIC-16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
数据速率:1.2 MbpsJESD-30 代码:R-PDSO-G16
长度:10.26 mm功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:2.67 mm标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:MODEM温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.49 mmBase Number Matches:1

FX614D4-LF-TR 数据手册

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Bell 202 Compatible Modem  
FX614  
FX614  
D4/P3  
Signal  
Description  
Pin No.  
Name  
VBIAS  
Type  
9
O/P  
Internally generated bias voltage, held at V /2  
DD  
when the device is not in 'Zero-Power' mode.  
Should be decoupled to V  
by a capacitor  
mounted close to the device pins.  
SS  
10  
11  
RXEQ  
TXD  
I/P  
I/P  
A logic level input for enabling/disabling the  
equaliser in the receive filter. See section 1.5.4.  
A logic level input for either the raw input to the  
FSK Modulator or data to be re-timed depending  
on the state of the M0, M1 and CLK inputs. See  
section 1.5.9.  
12  
13  
CLK  
RXD  
I/P  
A logic level input which may be used to clock  
data bits in or out of the FSK Data Retiming  
block.  
O/P  
A logic level output carrying either the raw  
output of the FSK Demodulator or re-timed  
characters depending on the state of the M0, M1  
and CLK inputs. See section 1.5.8.  
14  
15  
DET  
O/P  
O/P  
A logic level output of the on-chip Energy Detect  
circuit.  
RDYN  
"Ready for data transfer" output of the on-chip  
data retiming circuit. This open-drain active low  
output may be used as an Interrupt  
Request/Wake-up input to the associated mC.  
An external pull-up resistor should be connected  
between this output and V  
.
DD  
16  
VDD  
Power The positive supply rail. Levels and thresholds  
within the device are proportional to this voltage.  
Should be decoupled to V  
by a capacitor  
mounted close to the device pins.  
SS  
Notes: I/P  
=
Input  
O/P = Output  
This device is capable of detecting and decoding small amplitude signals. To achieve this VDD and VBIAS  
decoupling and protecting the receive path from extraneous in-band signals are very important. It is  
recommended that the decoupling capacitors are placed so that connections between them and the device  
pins are as short as practicable. A ground plane protecting the receive path will help attenuate interfering  
signals.  
ã 1997 Consumer Microcircuits Limited  
4
D/614/4  

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