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FTLX2072D333 PDF预览

FTLX2072D333

更新时间： 2024-10-29 01:19:07
品牌 Logo 应用领域
菲尼萨 - FINISAR /
页数 文件大小 规格书
11页 700K
描述
RoHS-6 Compliant 10Gb/s 10km Single Mode Bidirectional SFP Transceiver

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中文翻译

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FTLX2072D333 数据手册

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FTLX2072D3xx Product Specification  
I.  
Pin Descriptions  
Pin  
1
2
3
4
5
6
7
Symbol  
Name/Description  
Ref.  
1
2
3
2
2
2
4
VEET  
TFAULT  
TDIS  
SDA  
SCL  
Transmitter Ground  
Transmitter Fault  
Transmitter Disable. Laser output disabled on high or open.  
2-wire Serial Interface Data Line  
2-wire Serial Interface Clock Line  
Module Absent. Grounded within the module  
Rate Select 0. NC  
MOD_ABS  
RS0  
8
9
RX_LOS  
RS1  
Loss of Signal indication. Logic 0 indicates normal operation.  
Rate Select 1. NC  
5
4
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
VEER  
VEER  
RD-  
RD+  
VEER  
VCCR  
VCCT  
VEET  
Receiver Ground  
Receiver Ground  
Receiver Inverted DATA out. AC Coupled.  
Receiver Non-inverted DATA out. AC Coupled.  
Receiver Ground  
Receiver Power Supply  
Transmitter Power Supply  
Transmitter Ground  
1
1
1
1
1
TD+  
TD-  
VEET  
Transmitter Non-Inverted DATA in. AC Coupled.  
Transmitter Inverted DATA in. AC Coupled.  
Transmitter Ground  
Notes:  
1. Circuit ground is internally isolated from chassis ground.  
2. is an open collector/drain output, which should be pulled up with a 4.7k – 10k Ohms resistor on  
T
FAULT  
the host board if intended for use. Pull up voltage should be between 2.0V to Vcc + 0.3V. A high  
output indicates a transmitter fault caused by either the TX bias current or the TX output power  
exceeding the preset alarm thresholds. A low output indicates normal operation. In the low state, the  
output is pulled to <0.8V.  
3. Laser output disabled on TDIS >2.0V or open, enabled on TDIS <0.8V.  
4. Internally pulled down per SFF-8431 Rev 4.1.  
5. LOS is open collector output. Should be pulled up with 4.7k – 10kon host board to a voltage  
between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.  
Towards  
Bezel  
Towards  
ASIC  
Figure 1. Diagram of Host Board Connector Block Pin Numbers and Names.  
Finisar Corporation - June 2017  
Rev. A3  
Page 2  
1234567...11

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