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FT313HP-X PDF预览

FT313HP-X

更新时间: 2024-10-29 00:52:43
品牌 Logo 应用领域
飞特帝亚 - FTDI /
页数 文件大小 规格书
67页 1647K
描述
Single chip USB2.0 Hi-Speed compatible

FT313HP-X 数据手册

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Document No.: FT_000589  
FT313H USB2.0 HS Host Controller Datasheet Version 1.2  
Clearance No.: FTDI# 318  
Table of Contents  
1
Typical Applications...................................................................... 2  
1.1 Part Numbers...................................................................................... 2  
1.2 USB Compliant.................................................................................... 2  
FT313H Block Diagram ................................................................. 3  
Device Pin Out and Signal Description.......................................... 7  
3.1 Pin Out 64pin QFN ........................................................................... 7  
3.2 Pin Out 64pin LQFP.......................................................................... 8  
3.3 Pin Out 64pin TQFP.......................................................................... 9  
3.4 Pin Description ................................................................................. 10  
Function Description................................................................... 14  
4.1 Microcontroller Bus Interface ........................................................... 14  
4.2 SRAM bus interface mode ................................................................. 15  
4.3 NOR bus interface mode ................................................................... 16  
4.4 General multiplex bus interface mode .............................................. 16  
4.5 Interface mode lock.......................................................................... 16  
4.6 DMA controller.................................................................................. 16  
4.7 EHCI host controller ......................................................................... 17  
2
3
4
4.8 System clock..................................................................................... 17  
4.8.1 Phase Locked Loop (PLL) clock multiplier ...................................................................... 17  
4.9 Power management.......................................................................... 18  
4.9.1 Power up and reset sequence...................................................................................... 18  
4.9.2 Power supply............................................................................................................. 18  
4.9.3 ATX reference voltage ................................................................................................ 18  
4.9.4 Power modes ............................................................................................................ 18  
4.10  
BCD mode ...................................................................................... 19  
5
Host controller specific registers................................................ 20  
5.1 Overview of registers ....................................................................... 20  
5.2 EHCI operational registers................................................................ 21  
5.2.1 HCCAPLENGTH register (address = 00h)....................................................................... 21  
5.2.2 HCSPARAMS register (address = 04h).......................................................................... 21  
5.2.3 HCCPARAMS register (address = 08h).......................................................................... 22  
5.2.4 USBCMD register (address = 10h) ............................................................................... 22  
5.2.5 USBSTS register (address = 14h) ................................................................................ 24  
5.2.6 USBINTR register (address = 18h)............................................................................... 25  
5.2.7 FRINDEX register (address = 1Ch)............................................................................... 26  
5.2.8 PERIODICLISTADDR register (address = 24h) ............................................................... 26  
5.2.9 ASYNCLISTADDR register (address = 28h).................................................................... 26  
Copyright © 2013 Future Technology Devices International Limited  
4

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