FT28HC256
DEVICE OPERATION
Read
Write Operation Status Bits
The FT28HC256 provides the user two write operation
status bits. These can be used to optimised a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The
data bus will be in a high impedance state when either
OE or CE is HIGH.
Figure 1. Status Bit Assignment
I/O DP TB
5
4
3
2
1
0
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The FT28HC256 suppor ts
both a CE and WE controlled write cycle. That is, the
address is latched b y the f alling edge of either CE or
WE, whiche ver occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, which ever occurs first A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 3ms.
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O )
7
The FT28HC256 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
FT28HC256. This eliminates additional interrupt inputs
or external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
Page Write Operation
The page write feature of the FT28HC256 allows the
entire memory to be written in typically 0.8 seconds .
Page wr ite allows up to one hundred twenty-eight
bytes of data to be consecutively written to the
FT28HC256, prior to the commencement of the inter nal
programming cycle . The host can fetch data from
another device within the system during a page write
operation (change the source address), but the page
duce the complement of that data on I/O
data = 0xxx xxxx, read data = 1xxx xxxx).
(i.e., write
Once the
7
programming cycle is complete , I/O will reflect true
7
data.
Toggle Bit (I/O )
6
address (A through A ) for each subsequent valid
7
14
The FT28HC256 also provides another method for
determining when the internal write cycle is complete .
During the internal programming cycle I/O will toggle
write cycle to the part during this operation must be the
same as the initial page address.
6
The page write mode can be initiated dur ing any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle , started b y
the WE HIGH to LO W tr ansition, m ust begin within
100µs of the falling edge of the preceding WE. If a sub-
sequent WE HIGH to LOW transition is not detected
within 100µs , the internal automatic programming
cycle will commence . There is no page write window
limitation. Effectively the page write window is infinitel
wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease, and the device will be
accessible for additional read and write operations.
Characteristics subject to change without notice. 3 of 23
REV 1.0
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