FS6377-01

更新时间： 2024-01-04 06:43:11

品牌	Logo	应用领域
AMI		晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数	文件大小	规格书
21页	1496K
描述
Programmable 3-PLL Clock Generator IC

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技术参数
数据手册

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FS6377-01 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.75	JESD-30 代码：	R-PDSO-G16
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3/5 V	认证状态：	Not Qualified
子类别：	Clock Generators	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6377-01 数据手册

Data Sheet

FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC

5.1.2 START Data Transfer

A high to low transition of the SDA line while the SCL input

is high indicates a START condition. All commands to the

device must be preceded by a START condition.

5.1.3 STOP Data Transfer

A low to high transition of the SDA line while SCL is held

high indicates a STOP condition. All commands to the

device must be followed by a STOP condition.

5.1.4 Data Valid

The state of the SDA line represents valid data if the SDA

line is stable for the duration of the high period of the SCL

line after a START condition occurs. The data on the SDA

line must be changed only during the low period of the

SCL signal. There is one clock pulse per data bit.

terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions is

determined by the master device, and can continue

indefinitely. However, data that is overwritten to the device

after the first sixteen bytes will overflow into the first

overwritten fashion.

Each data transfer is initiated by a START condition and

5.1.5 Acknowledge

When addressed, the receiving device is required to

generate an acknowledge after each byte is received. The

master device must generate an extra clock pulse to

coincide with the acknowledge bit. The acknowledging

device must pull the SDA line low during the high period of

the master acknowledge clock pulse. Setup and hold

times must be taken into account.

The master must signal an end of data to the slave by not

generating an acknowledge bit on the last byte that has

been read (clocked) out of the slave. In this case, the

slave must leave the SDA line high to enable the master

to generate a STOP condition.

5.2 I²C-bus Operation

All programmable registers can be accessed randomly or

sequentially via this bi-directional two wire digital interface.

The device accepts the following I²C-bus commands.

5.2.1 Slave Address

After generating a START condition, the bus master

broadcasts a seven-bit slave address followed by a R/W

bit. The address of the device is:

where X is controlled by the logic level at the ADDR pin.

The variable ADDR bit allows two different devices to exist

on the same bus. Note that every device on an I²C-bus

must have a unique address to avoid bus conflicts. The

default address sets A2 to one via the pull-up on the ADDR

pin.

5.2.2 Random Register Write Procedure

Random write operations allow the master to directly write

to any register. To initiate a write procedure, the R/W bit

that is transmitted after the seven-bit device address is a

logic-low. This indicates to the addressed slave device that

a register address will follow after the slave device

acknowledges its device address. The register address is

written into the slave's address pointer. Following an

acknowledge by the slave, the master is allowed to write

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与FS6377-01相关器件

型号	品牌	描述	获取价格	数据表
FS6377-01G	AMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G-XTD	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G-XTP	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01I	ONSEMI	暂无描述	获取价格
FS6377-01IG	AMI	Clock Generator, 150MHz, CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16	获取价格
FS6377-01IG-XTD	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格

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