FS6377-01

更新时间： 2024-02-19 05:45:19

品牌	Logo	应用领域
AMI		晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数	文件大小	规格书
21页	1496K
描述
Programmable 3-PLL Clock Generator IC

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技术参数
数据手册

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FS6377-01 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.75	JESD-30 代码：	R-PDSO-G16
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3/5 V	认证状态：	Not Qualified
子类别：	Clock Generators	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6377-01 数据手册

Data Sheet

FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC

eight bits of data into the addressed register. A final

acknowledge is returned by the device, and the master

generates a STOP condition.

If either a STOP or a repeated START condition occurs

during a register write, the data that has been transferred

is ignored.

5.2.3 Random Register Read Procedure

Random read operations allow the master to directly read

from any register. To perform a read procedure, the R/W

bit that is transmitted after the seven-bit address is a logic-

low, as in the register write procedure. This indicates to the

addressed slave device that a register address will follow

after the slave device acknowledges its device address.

The register address is then written into the slave's

address pointer.

Following an acknowledge by the slave, the master gen-

erates a repeated START condition. The repeated START

terminates the write procedure, but not until after the

slave's address pointer is set. The slave address is then

resent, with the R/W bit set this time to a logic-high,

indicating to the slave that data will be read. The slave will

acknowledge the device address, and then transmits the

eight-bit word. The master does not acknowledge the

transfer but does generate a STOP condition.

5.2.4 Sequential Register Write Procedure

Sequential write operations allow the master to write to

each register in order. The register pointer is automatically

incremented after each write. This procedure is more

efficient than the random register write if several registers

must be written.

slave, the master is allowed to write up to sixteen bytes of

data into the addressed register before the register

address pointer overflows back to the beginning address.

An acknowledge by the device between each byte of data

must occur before the next data byte is sent.

To initiate a write procedure, the R/W bit that is transmitted

after the seven-bit device address is a logic-low. This

indicates to the addressed slave device that a register

address will follow after the slave device acknowledges its

device address. The register address is written into the

slave's address pointer. Following an acknowledge by the

Registers are updated every time the device sends an

acknowledge to the host. The register update does not

wait for the STOP condition to occur. Registers are

therefore updated at different times during a sequential

5.2.5 Sequential Register Read Procedure

Sequential read operations allow the master to read from

each register in order. The register pointer is automatically

incremented by one after each read. This procedure is

more efficient than the random register read if several

registers must be read.

Following an acknowledge by the slave, the master

generates a repeated START condition. The repeated

START terminates the write procedure, but not until after

the slave's address pointer is set. The slave address is

then resent, with the R/W bit set this time to a logic-high,

indicating to the slave that data will be read. The slave will

acknowledge the device address, and then transmits all

16 bytes of data starting with the initial addressed register.

The register address pointer will overflow if the initial

data, the master does not acknowledge the transfer but

does generate a STOP condition.

To perform a read procedure, the R/W bit that is

transmitted after the seven-bit address is a logic-low, as in

the register write procedure. This indicates to the

addressed slave device that a register address will follow

after the slave device acknowledges its device address.

The register address is then written into the slave's

address pointer.

AMI Semiconductor

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与FS6377-01相关器件

型号	品牌	获取价格	描述	数据表
FS6377-01G	AMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01G-XTD	ONSEMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01G-XTP	ONSEMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01I	ONSEMI	获取价格	暂无描述
FS6377-01IG	AMI	获取价格	Clock Generator, 150MHz, CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16
FS6377-01IG-XTD	ONSEMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01IG-XTP	ONSEMI	获取价格	Programmable 3-PLL Clock Generator IC
FS6377-01ITR	AMI	获取价格	Clock Generator, CMOS, PDSO16,
FS650R08A4P2	INFINEON	获取价格	Wave baseplate
FS660R08A6P2FB	INFINEON	获取价格	Short Tabs

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