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FS6377-01

更新时间: 2024-02-09 10:04:47
品牌 Logo 应用领域
AMI 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
21页 1496K
描述
Programmable 3-PLL Clock Generator IC

FS6377-01 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.75JESD-30 代码:R-PDSO-G16
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3.3/5 V认证状态:Not Qualified
子类别:Clock Generators表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

FS6377-01 数据手册

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Data Sheet  
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC  
3.1.1 Reference Divider  
The reference divider is designed for low phase jitter. The  
divider accepts the output of the reference oscillator and  
provides a divided-down frequency to the PFD. The  
reference divider is an 8-bit divider, and can be  
programmed for any modulus from 1 to 255 by  
programming the equivalent binary value. A divide-by-256  
can also be achieved by programming the eight bits to  
00h.  
3.1.2 Feedback Divider  
The feedback divider is based on a dual-modulus pre-  
scaler technique. The technique allows the same  
granularity as a fully programmable feedback divider,  
while still allowing the programmable portion to operate at  
low speed. A high-speed pre-divider (also called a  
prescaler) is placed between the VCO and the  
programmable feedback divider because of the high  
speeds at which the VCO can operate. The dual-modulus  
technique insures reliable operation at any speed that the  
VCO can achieve and reduces the overall power  
consumption of the divider.  
To understand the operation, refer to Figure 4. The M-  
counter (with a modulus always equal to M) is cascaded  
with the dual-modulus prescaler. The A-counter controls  
the modulus of the prescaler. If the value programmed into  
the A-counter is A, the prescaler will be set to divide by  
N+1 for A prescaler outputs. Thereafter, the prescaler  
divides by N until the M-counter output resets the A-  
counter, and the cycle begins again. Note that N=8 and A  
and M are binary numbers.  
Suppose that the A-counter is programmed to zero. The  
modulus of the prescaler will always be fixed at N; and the  
entire modulus of the feedback divider becomes MxN.  
For example, a fixed divide-by-eight could be used in the  
feedback divider. Unfortunately, a divide-by-eight would  
limit the effective modulus of the entire feedback divider to  
multiples of eight. This limitation would restrict the ability of  
the PLL to achieve a desired input-frequency-to-output-  
frequency ratio without making both the reference and  
feedback divider values comparatively large.  
Next, suppose that the A-counter is programmed to a one.  
This causes the prescaler to switch to a divide-by-N+1 for  
its first divide cycle and then revert to a divide-by-N. In  
effect, the A-counter absorbs (or "swallows") one extra  
clock during the entire cycle of the feedback divider. The  
overall modulus is now seen to be equal to MxN+1.  
A large feedback modulus means that the divided VCO  
frequency is relatively low, requiring a wide loop band-  
width to permit the low frequencies. A narrow loop band-  
width tuned to high frequencies is essential to minimizing  
jitter; therefore, divider moduli should always be as small  
as possible.  
This example can be extended to show that the feedback  
divider modulus is equal to MxN+A, where A<M.  
Dual  
Modulus  
Prescaler  
fVCO  
M
fPD  
Counter  
FBKDIV[2:0]  
FBKDIV[10:3]  
A
Counter  
Figure 4: Feedback Divider  
AMI Semiconductor  
www.amis.com  
3

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