Datasheet > FS6370-01-XTP

FS6370-01-XTP

更新时间： 2024-01-04 09:38:45

品牌	Logo	应用领域
AMI		光电二极管
页数	文件大小	规格书
24页	328K
描述
Clock Generator, CMOS, PDSO16,

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技术参数
数据手册

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FS6370-01-XTP 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP16,.25	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	R-PDSO-G16
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3/5 V	认证状态：	Not Qualified
子类别：	Clock Generators	最大压摆率：	43 mA
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

FS6370-01-XTP 数据手册

Data Sheet

FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator IC

3.0 Functional Block Description

3.1 Phase Locked Loops (PLLs)

Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by

a ratio of integers. This frequency multiplication is exact.

As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled

oscillator (VCO), and a feedback divider.

REF

During operation, the reference frequency (f ), generated by the on-board crystal oscillator, is first reduced by the reference divider. The divider value is

often referred to as the modulus, and is denoted as N for the reference divider. The divided reference is fed into the PFD.

VCO

The PFD controls the frequency of the VCO (f ) through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable

frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider (the modulus is denoted by N ) to close

the loop.

LFTC

Loop

REFDIV[7:0]

Filter

f_REF

Reference

Divider

(N_R)

f_VCO

Phase-

Frequency

Detector

Voltage

Controlled

Oscillator

Charge

Pump

DOWN

FBKDIV[10:0]

f_PD

Feedback

Divider (N_F)

Figure 3: PLL Block Diagram

The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the

PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:





N_F

N_R





f_VCO

= f_REF





3.1.1 Reference Divider

The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to

the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value.

A divide-by-256 can also be achieved by programming the eight bits to 00h.

3.1.2 Feedback Divider

The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully programmable feedback divider,

while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a pre-scaler) is placed between the VCO and

the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at

any speed that the VCO can achieve and reduces the overall power consumption of the divider.

AMI Semiconductor - Rev. 2.0, Mar. 05

www.amis.com.

1 234 5 6 7...24

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与FS6370-01-XTP相关器件

型号	品牌	描述	获取价格	数据表
FS6377	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01	AMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G	AMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G-XTD	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G-XTP	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01I	ONSEMI	暂无描述	获取价格

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