Data Sheet
FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator IC
Figure 16: Post Divider Menu
Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider
box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long
as mux B is the PLL C output.
Clicking on post divider A reveals a pull-down menu provided to permit adjustment of the post divider value independently of the PLL screen. A typical
menu is shown in Figure 16. The range of possible post divider values is also given in Table 7.
The EEPROM settings are shown to the left in the screen shown in Figure 14. Clicking on a register location displays a screen shown in Figure 17. Individual
bits can be poked, or the entire register value can be changed.
Figure 17: Register Screen
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