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FM25C160-GTR PDF预览

FM25C160-GTR

更新时间： 2024-01-23 14:45:50
品牌 Logo 应用领域
铁电 - RAMTRON 光电二极管内存集成电路
页数 文件大小 规格书
13页 297K
描述
Memory Circuit, 2KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8

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FM25C160-GTR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：unknownHTS代码：8542.32.00.71
风险等级：5.06JESD-30 代码：R-PDSO-G8
长度：4.9 mm内存密度：16384 bit
内存集成电路类型：MEMORY CIRCUIT内存宽度：8
功能数量：1端子数量：8
字数：2048 words字数代码：2000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2KX8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

FM25C160-GTR 数据手册

 浏览型号FM25C160-GTR的Datasheet PDF文件第4页浏览型号FM25C160-GTR的Datasheet PDF文件第5页浏览型号FM25C160-GTR的Datasheet PDF文件第6页浏览型号FM25C160-GTR的Datasheet PDF文件第8页浏览型号FM25C160-GTR的Datasheet PDF文件第9页浏览型号FM25C160-GTR的Datasheet PDF文件第10页 
FM25C160  
The BP1 and BP0 bits and the Write Enable Latch  
are the only mechanisms that protect the memory  
from writes. The remaining write protection features  
protect inadvertent changes to the block protect bits.  
This scheme provides a write protection mechanism,  
which can prevent software from writing the memory  
under any circumstances. This occurs if the BP1 and  
BP0 are set to 1, the WPEN bit is set to 1, and /WP is  
set to 0. This occurs because the block protect bits  
prevent writing memory and the /WP signal in  
hardware prevents altering the block protect bits (if  
WPEN is high). Therefore in this condition, hardware  
must be involved in allowing a write operation. The  
following table summarizes the write protection  
conditions.  
The WPEN bit controls the effect of the hardware  
/WP pin. When WPEN is low, the /WP pin is  
ignored. When WPEN is high, the /WP pin controls  
write access to the status register. Thus the Status  
register is write protected if WPEN=1 and /WP=0.  
Table 4. Write Protection  
WEL  
WPEN  
/WP  
X
Protected Blocks  
Protected  
Unprotected Blocks  
Protected  
Unprotected  
Unprotected  
Unprotected  
Status Register  
Protected  
0
1
1
1
X
0
X
Protected  
Unprotected  
Protected  
1
0
1
Protected  
Protected  
1
Unprotected  
Memory Operation  
Read Operation  
The SPI interface, with its relatively high maximum  
clock frequency, highlights the fast write capability  
of the FRAM technology. Unlike SPI-bus  
EEPROMs, the FM25C160 can perform sequential  
writes at bus speed. No page register is needed and  
any number of sequential writes may be performed.  
After the falling edge of /CS, the bus master can issue  
a READ op-code. Following this instruction is a two-  
byte address value. The upper 5-bits of the address  
are don’t care. In total, the 11-bits specify the address  
of the first byte of the read operation. After the op-  
code and address are complete, the SI line is ignored.  
The bus master issues 8 clocks, with one bit read out  
for each. Addresses are incremented internally as  
long as the bus master continues to issue clocks. If  
the last address of 7FFh is reached, the counter will  
roll over to 0000h. Data is read MSB first. The rising  
edge of /CS terminates a READ op-code operation.  
The bus configuration for read and write operations is  
shown below.  
Write Operation  
All writes to the memory array begin with a WREN  
op-code. The next op-code is the WRITE instruction.  
This op-code is followed by a two-byte address  
value. The upper 5-bits of the address are don’t care.  
In total, the 11-bits specify the address of the first  
byte of the write operation. Subsequent bytes are data  
and they are written sequentially. Addresses are  
incremented internally as long as the bus master  
continues to issue clocks. If the last address of 7FFh  
is reached, the counter will roll over to 0000h. Data is  
written MSB first.  
Hold  
The /HOLD pin can be used to interrupt a serial  
operation without aborting it. If the bus master takes  
the /HOLD pin low while SCK is low, the current  
operation will pause. Taking the /HOLD pin high  
while SCK is low will resume an operation. The  
transitions of /HOLD must occur while SCK is low,  
but the SCK pin can toggle during a hold state.  
Unlike EEPROMs, any number of bytes can be  
written sequentially and each byte is written to  
memory immediately after it is clocked in (after the  
8th clock). The rising edge of /CS terminates a  
WRITE op-code operation.  
Rev. 3.3  
Feb. 2011  
Page 7 of 13  
1...45678910...13

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