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FM25C160-G PDF预览

FM25C160-G

更新时间: 2023-04-15 00:00:00
品牌 Logo 应用领域
铁电 - RAMTRON 光电二极管
页数 文件大小 规格书
13页 297K
描述
Memory Circuit, 2KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8

FM25C160-G 数据手册

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FM25C160  
Figure 9. Memory Write  
Figure 10. Memory Read  
should not be located within the same row. In the  
FM25C160, there are 512 rows each 32 bits wide.  
Regardless, FRAM read and write endurance is  
effectively unlimited at the 20 MHz clock speed.  
Even at 2000 accesses per second to the same row, 15  
years time will elapse before 1012 endurance cycles  
occur.  
Endurance  
Internally, a FRAM operates with a read and restore  
mechanism similar to  
a
DRAM. Therefore,  
endurance cycles are applied for each access: read or  
write. The FRAM architecture is based on an array of  
rows and columns. Each access causes an endurance  
cycle for an entire row. Therefore, data locations  
targeted for substantially differing numbers of cycles  
Rev. 3.3  
Feb. 2011  
Page 8 of 13  

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