Datasheet > FLLXT385BE

FLLXT385BE

更新时间： 2024-11-15 19:59:03

品牌	Logo	应用领域
英特尔 - INTEL		PC
页数	文件大小	规格书
134页	1516K
描述
Telecom IC, CMOS, PBGA160

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技术参数
数据手册

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FLLXT385BE 技术参数

生命周期：	Obsolete	包装说明：	BGA, BGA160,14X14,40
Reach Compliance Code：	unknown	风险等级：	5.84
运营商类型：	CEPT PCM-30/E-1	JESD-30 代码：	S-PBGA-B160
端子数量：	160	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA160,14X14,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	3.3,3.3/5 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

FLLXT385BE 数据手册

Intel^®LXT385 Quad E1 Short-Haul PCM

Transceiver with Jitter Attenuation (JA)

Datasheet

Product Features

■ Quad E1 Pulse-Code Modulation (PCM)

Transceiver with Jitter Attenuation for use

in 2.048 Mbps (E1) applications

■ 8 fully-independent receiver/transmitters

■ Support for E1 standards:

■ Transmitters

—Transmit waveform shaping meets ITU

G.703 specifications

—Exceeds ETSI ETS 300 166 transmit

return-loss specifications

—Exceeds ETSI ETS 300 166

—Low-impedance transmit drivers,

independent of transmit pattern and

supply-voltage variations.

■ Meets ETS 300 233Low-power single-rail

3.3-V CMOS power supply, with 5-V

tolerant I/Os

—Low-current transmit output option that

can reduce power dissipation by up to

15%. By changing the LXT385

transceiver output transformer ratio

from 1:2 to 1:1.7, the savings occur

whether TVCC is at 5V or 3.3V. 90 mW

per channel (typical). See Table 62

“Intel^®LXT385 Transceiver Power

Consumption” on page 104 and

Table 64 “Load³Power Consumption”

on page 105.

■ Jitter attenuation

—Crystal-less

—Digital clock recovery PLL

—Referenced to 2.048-MHz clock.

Normal operation requires only MCLK.

Does not require a reference clock

frequency higher than the line

frequency.

—Can be switched between receive and

transmit path

■ HDB3 AMI line encoder/decoder

■ LOS per ITU G.775 and ETS 300 233

■ Diagnostics:

—Meets ETSI CTR12/13, ITU G.736,

G.742, and G.823

—Optimized for Synchronous Digital

Hierarchy (SDH) applications, meets

ITU G.783 mapping jitter standard

—Can be configured for G.722-compliant,

non-intrusive performance (protected)

monitoring points

—Constant throughput delay

—Industry-standard P1149.1 JTAG

Boundary Scan test port

■ Differential receiver architecture

—High margin for noise interference

—Operates at >12 dB of cable attenuation

■ Intel^®Hitless Protection Switching

■ Intel^®/ Motorola* 8-bit parallel processor

interface or 4 wire serial control interface

■ Hardware and Software control modes

■ Operating temperature -40 °C to 85 °C

■ 160-ball PBGA or 144-pin LQFP packages

—Eliminates mechanical relays for

redundancy 1+1 protection applications

—Increases quality of service

Applications

■ SDH tributary interfaces

■ Digital cross connects

■ Microwave transmission systems

■ M13, E1-E3 MUX

■ Public/private switching trunk line interfaces

Document Number: 249252

Revision Number: 004

Revision Date: July 26, 2004

12 3 4 5 6 7...134

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