Datasheet > FEDL7204-003-01

FEDL7204-003-01

更新时间： 2024-11-14 01:19:55

品牌	Logo	应用领域
LAPIS		/
页数	文件大小	规格书
214页	2223K
描述
VoIP CODEC

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FEDL7204-003-01 数据手册

FEDL7204-003-02

Issue Date: Oct 14, 2011

ML7204-003

VoIP CODEC

GENERAL DESCRIPTION

The ML7204-003 is a speech CODEC for VoIP. As a speech CODEC, this LSI allows selection of

G.729.A/G711 and supports the PLC (Packet Loss Concealment) function.

With an echo canceler that handles 32 ms-delay and FSK detection/generation, DTMF detection/generation, and

tone detection/generation functions, the ML7204-003 is the most suitable LSI for adding the VoIP function to

TAs and routers.

FEATURES

 Power supply voltage

Digital power supply voltage (DVDD0, 1, 2):

Analog power supply voltage (AVDD):

 Speech CODEC:

3.0 to 3.6 V

G.729.A (8 kbps)/G.711 (64 kbps) -law and A-law (supports individual setting for transmission and

reception)

Supports ITU-T G.711 Appendix 1 compliant PLC (Packet Loss Concealment) function

Supports the 2-channel processing function (for 3-way communication)

 Built-in FIFO buffer (640 bytes) for transmission/reception data transfer

Allows selection of Frame/DMA (slave) interface

 Provided with echo canceler for handling 32 ms delay and Range Controllers

 DTMF detection

 DTMF generation (the tone generation function enables generation of DTMF signals)

 Tone detection:

 Tone generation:

 FSK detection

2 types (1650 Hz and 2100 Hz: Detection frequency can be changed)

2 types

 FSK generation

 Built-in 16-bit timer:

1 channel

 Dial pulse detection function (secondary function of general-purpose I/O ports)

 Dial pulse transmission function (secondary function of general-purpose I/O ports)

 General-purpose I/O ports : Equipped with 7 ports (with some of them having secondary function allocation)

 Two types of built-in linear PCM CODEC (CODEC_A and CODEC_B)

 Analog interface

CODEC_A side: Incorporates one type each of input amplifier and output amplifier (10 k driving)

CODEC_B side: Incorporates one type each of input amplifier and output amplifier (10 k driving)

 PCM interface coding format:

Allows selection of 16-bit linear/G.711 (64 kbps) -law or A-law

 PCM serial transmission rate: 64 kHz to 2.048 MHz (fixed to 2.048 MHz for output)

 PCM time slot assignment function (allows up to 2 slots for input and 1 slot for output individually)

When set to -law/A-law: Supports up to 32 slots (BCLK: 2.048 MHz)

When set to 16-bit linear: Supports up to 16 slots (BCLK: 2.048 MHz)

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与FEDL7204-003-01相关器件

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FEDL7204-003-02	LAPIS	获取价格	VoIP CODEC
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FEDL7344CJ-05	LAPIS	获取价格	Sub-GHz(160MHz to 510MHz) band short range wireless transceiver IC
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