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FCT162373ATPACTG4 PDF预览

FCT162373ATPACTG4

更新时间: 2024-10-28 10:31:55
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件
页数 文件大小 规格书
14页 694K
描述
FCT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 0.240 INCH, 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-48

FCT162373ATPACTG4 数据手册

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Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16373T  
CY74FCT162373T  
SCCS054C - August 1994 - Revised October 2003  
16-Bit Latches  
Features  
Functional Description  
• Ioff supports partial-power-down mode operation  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
CY74FCT16373T and CY74FCT162373T are 16-bit D-type  
latches designed for use in bus applications requiring high  
speed and low power. These devices can be used as two  
independent 8-bit latches or as a single 16-bit latch by  
connecting the Output Enable (OE) and Latch (LE) inputs.  
Flow-through pinout and small shrink packaging aid in  
simplifying board layout.  
This device is fully specified for partial-power-down  
applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device  
when it is powered down.  
• Industrial temperature range of 40˚C to +85˚C  
• VCC = 5V ± 10%  
CY74FCT16373T Features:  
The CY74FCT16373T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
The CY74FCT162373T has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162373T is ideal for driving transmission lines.  
CY74FCT162373T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
Pin Configuration  
Logic Block Diagrams  
SSOP/TSSOP/TVSOP  
OE  
1
Top View  
1
48  
47  
46  
45  
44  
43  
42  
41  
OE  
O
LE  
1
1
1
LE  
D
1
1
2
1
1
2
O
D
2
3
1
1
D
C
D
1
1
GND  
O
4
GND  
D
O
1
1
5
1
1
3
4
1
1
3
4
O
D
6
V
CC  
V
CC  
7
O
D
1
1
5
6
1
1
5
6
8
O
D
9
40  
39  
38  
TO 7 OTHERCHANNELS  
GND  
GND  
10  
11  
O
D
1
1
7
8
1
1
7
8
FCT162373-1  
O
D
12  
13  
37  
36  
35  
34  
33  
OE  
LE  
2
O
O
D
D
2
2
1
2
2
1
14  
15  
16  
17  
18  
2
2
GND  
GND  
2
O
3
O
4
D
D
2
2
3
D
C
D
1
32  
31  
30  
29  
28  
27  
26  
25  
2
2
2
4
O
1
2
V
CC  
V
CC  
O
5
D
5
19  
20  
21  
22  
23  
24  
2
2
2
2
O
6
D
6
GND  
O
GND  
D
2
2
7
8
2
7
8
TO 7 OTHERCHANNELS  
O
D
2
2
OE  
LE  
2
FCT162373-2  
FCT162373-3  
Copyright © 2003, Texas Instruments Incorporated  

FCT162373ATPACTG4 替代型号

型号 品牌 替代类型 描述 数据表
74ABT16373ADGGRG4 TI

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