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FAN6555 PDF预览

FAN6555

更新时间: 2024-09-26 22:40:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 稳压器开关式稳压器或控制器电源电路开关式控制器双倍数据速率
页数 文件大小 规格书
12页 118K
描述
2A DDR Bus Termination Regulator

FAN6555 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Is Samacsys:NBase Number Matches:1

FAN6555 数据手册

 浏览型号FAN6555的Datasheet PDF文件第2页浏览型号FAN6555的Datasheet PDF文件第3页浏览型号FAN6555的Datasheet PDF文件第4页浏览型号FAN6555的Datasheet PDF文件第5页浏览型号FAN6555的Datasheet PDF文件第6页浏览型号FAN6555的Datasheet PDF文件第7页 
www.fairchildsemi.com  
FAN6555  
2A DDR Bus Termination Regulator  
Features  
Description  
• Can source and sink up to 2A continous, 3A peak  
• No heatsink required  
• Integrated Power MOSFETs  
• Generates termination voltages for DDR SDRAM  
• VREF input available for external voltage divider  
• Separate voltages for VCCQ and PVDD  
• Buffered VREF output  
• VOUT of 3ꢀ or less at 2A  
• Minimum external components  
• 16-pin SOIC package  
The FAN6555 switching regulator is designed to convert  
voltage supplies ranging from 2.3V to 4V into a desired out-  
put voltage or termination voltage for DDR SDRAM mem-  
ory. The FAN6555 can be implemented to produce regulated  
output voltages in two different modes. In the default mode,  
when the VREF pin is open, the FAN6555 output voltage is  
50ꢀ of the voltage applied to VCCQ. The FAN6555 can also  
be used to produce various user-defined voltages by forcing a  
voltage on the VREFIN pin. In this case, the output voltage  
follows the input VREFIN voltage. The switching regulator  
is capable of sourcing or sinking up to 2A of current while  
regulating an output VTT voltage to within 3ꢀ or less.  
Transient output currents of 3A can also be accommodated.  
• -40°C to +85°C operating temperature range  
• Shutdown for standby or suspend mode operation  
• Thermal Shutdown 130ºC  
The FAN6555 can also be used in conjunction with series  
termination resisitors to provide an excellent voltage source  
for active termination schemes of high speed transmission  
lines as those seen in high speed memory buses and distrib-  
uted backplane designs.  
Block Diagram  
9
15  
16  
14  
1
12  
2
7
V
AV  
VREF  
OUT  
V
SHDN  
PV  
PV  
DD2  
V
CCQ  
CC  
DD  
DD1  
DD  
V
OUT  
OSCILLATOR/  
RAMP  
L1  
(V  
)
3
6
GENERATOR  
200kΩ  
Q
Q
S
R
+
V
OUT  
L2  
V
BUFFER  
REF  
(V  
)
+
VREF  
IN  
ERROR AMP  
11  
13  
RAMP  
COMPARATOR  
+
200kΩ  
AGND  
V
D
P
P
GND2  
FB  
GND  
GND1  
10  
8
4
5
REV. 1.1.3 8/4/03  

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