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FAN3121CMPX PDF预览

FAN3121CMPX

更新时间： 2024-02-23 14:30:50
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器MOSFET驱动器栅极驱动程序和接口接口集成电路栅极驱动
页数 文件大小 规格书
21页 1334K
描述
Single 9A High-Speed, Low-Side Gate Driver

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FAN3121CMPX 技术参数

是否无铅：不含铅生命周期：Active
包装说明：SOP, SOP8,.25Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
Factory Lead Time：1 week风险等级：1.39
Is Samacsys：N内置保护：UNDER VOLTAGE
高边驱动器：NO接口集成电路类型：BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码：R-PDSO-G8JESD-609代码：e4
长度：5 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
输出电流流向：SOURCE AND SINK封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：12 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：MOSFET Drivers最大压摆率：0.9 mA
最大供电电压：18 V最小供电电压：4.5 V
标称供电电压：12 V表面贴装：YES
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
断开时间：0.035 µs接通时间：0.035 µs
宽度：4 mmBase Number Matches：1

FAN3121CMPX 数据手册

 浏览型号FAN3121CMPX的Datasheet PDF文件第12页浏览型号FAN3121CMPX的Datasheet PDF文件第13页浏览型号FAN3121CMPX的Datasheet PDF文件第14页浏览型号FAN3121CMPX的Datasheet PDF文件第16页浏览型号FAN3121CMPX的Datasheet PDF文件第17页浏览型号FAN3121CMPX的Datasheet PDF文件第18页 
Figure 47 shows the pulsed gate drive current path  
when the gate driver is supplying gate charge to turn  
the MOSFET on. The current is supplied from the local  
bypass capacitor CBYP and flows through the driver to  
the MOSFET gate and to ground. To reach the high  
peak currents possible with the FAN312x family, the  
resistance and inductance in the path should be  
minimized. The localized CBYP acts to contain the high  
peak current pulses within this driver-MOSFET circuit,  
preventing them from disturbing the sensitive analog  
circuitry in the PWM controller.  
VDD  
Turn-on threshold  
IN-  
VDD  
VDS  
IN+  
(VDD  
)
CBYP  
FAN3121/2  
OUT  
PWM  
Figure 47. Current Path for MOSFET Turn-On  
Figure 50. Inverting Startup Waveforms  
Figure 48 shows the path the current takes when the gate  
driver turns the MOSFET off. Ideally, the driver shunts the  
current directly to the source of the MOSFET in a small  
circuit loop. For fast turn-off times, the resistance and  
inductance in this path should be minimized.  
At power up, the FAN3122 non-inverting driver, shown  
in Figure 51, holds the output LOW until the VDD voltage  
reaches the UVLO turn-on threshold, as indicated in  
Figure 52. The OUT pulses magnitude follow VDD  
magnitude until steady-state VDD is reached.  
VDD  
VDS  
VDD  
CBYP  
IN  
OUT  
FAN3121/2  
Figure 51. Non-Inverting Driver  
PWM  
VDD  
Figure 48. Current Path for MOSFET Turn-Off  
Turn-on threshold  
Operational Waveforms  
At power up, the FAN3121 inverting driver shown in  
Figure 49 holds the output LOW until the VDD voltage  
reaches the UVLO turn-on threshold, as indicated in  
Figure 50. This facilitates proper startup control of low-  
side N-channel MOSFETs.  
IN-  
VDD  
IN+  
IN  
OUT  
OUT  
Figure 49. Inverting Configuration  
The OUT pulses’ magnitude follows VDD magnitude with  
the output polarity inverted from the input until steady-  
state VDD is reached.  
Figure 52. Non-Inverting Startup Waveforms  
© 2008 Fairchild Semiconductor Corporation  
FAN3121 / FAN3122 • Rev. 1.0.0  
www.fairchildsemi.com  
15  
1...12131415161718...21

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