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FAGD1659048BA PDF预览

FAGD1659048BA

更新时间: 2024-10-28 21:17:59
品牌 Logo 应用领域
英特尔 - INTEL ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
12页 177K
描述
Support Circuit, 1-Func, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-48

FAGD1659048BA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:HLFQFP,
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.8
JESD-30 代码:S-PQFP-G48长度:7 mm
湿度敏感等级:1功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-5 °C封装主体材料:PLASTIC/EPOXY
封装代码:HLFQFP封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:1.6 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:OTHER
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

FAGD1659048BA 数据手册

 浏览型号FAGD1659048BA的Datasheet PDF文件第2页浏览型号FAGD1659048BA的Datasheet PDF文件第3页浏览型号FAGD1659048BA的Datasheet PDF文件第4页浏览型号FAGD1659048BA的Datasheet PDF文件第5页浏览型号FAGD1659048BA的Datasheet PDF文件第6页浏览型号FAGD1659048BA的Datasheet PDF文件第7页 
1.244 GHz  
Generic PLL  
Clock  
an Intel company  
Synthesiser  
GD16590  
Preliminary  
General Information  
Features  
l
The GD16590 is a generic PLL clock  
synthesiser. The device targets clock dis-  
tribution in SDH/SONET telecommunica-  
tion systems but is well suited for a wide  
range of applications requiring high per-  
formance high-speed clock synthesis.  
As an option the GD16590 may be oper-  
ated with an external Voltage Controlled  
Crystal Oscillator for applications de-  
manding a high-Q oscillator.  
Six separate differential clock outputs  
from the PLL at :  
1,244.16 / 622.08 MHz  
1,244.16 / 622.08 MHz  
622.08 / 311.04 MHz  
311.04 / 155.52 MHz  
155.52 / 77.76 MHz  
77.76 / 38.88 MHz  
all with separate enable.  
The reference clock may range from 19  
to 622 MHz.  
The device implements a fully integrated  
multiplying PLL including:  
The GD16590 requires a single +3.3 V  
power supply.  
u
An on-chip Voltage Controlled  
Oscillator (VCO)  
l
Three independent selectable  
reference clock inputs.  
u
Phase-Frequency Detector  
Programmable frequency dividers  
The device is housed in a 48 TQFP  
7 × 7 mm thermally enhanced package.  
u
l
(prescalers).  
The loop-filter is external in order to opti-  
mise the PLL for different applications.  
Intrinsic jitter: 0.005 UIPP @ 622 MHz.  
l
Low phase skew between output  
clocks: < 200 ps.  
l
Optional external VCXO possible.  
VCXO  
R1  
l
Simple external loop filter.  
C1  
OCHP  
VCTL  
DCCAL  
VCXO  
× 3  
l
Lock detect output signal.  
CKREFx  
CHAP  
50R  
50R  
VCO  
VCCA  
VCC  
V
R
D
U
Div.  
2, 4  
Select  
3:1  
CKRTx  
PFC  
l
Single power supply: +3.3 V.  
2.5 GHz  
CKREFxN  
VEE  
/2  
l
Low power operation: 0.54 W (Typ.).  
VCOSEL1  
Select  
4:1  
l
Package: 48 pin TQFP (7 × 7 mm).  
VCOSEL2  
NLDET  
CHAP  
XOR  
SEL1  
SEL2  
C2  
Div.  
1, 2,  
4, 8, 16,  
32, 64  
NLOCK  
Applications  
× 6  
× 7  
OUTENAx  
l
× 7  
Select  
7:1  
FOUTx  
FOUTxN  
Tele Communications systems:  
SDH  
SONET  
× 3  
l
l
Datacom  
× 3  
SEL3/4/5  
High-speed general clock distribution.  
Data Sheet Rev.: 13  

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