3.3V HCMOS Automotive Grade SMD Oscillator
RoHS Compliant / Pꢁ Free / REACH Compliant
Model: FA530 SERIES
Rev. 2/27/2012
Page 1 of 2
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FEATURES
• AEC-Q200 Qualified
• TS-16949 Certified
• Temperature range from -40ºC ~ +125ºC
• Seam Seal
• Tape and Reel (1,000 pcs. STD)
• PART ꢀUMbER SELECTIOꢀ
5.2 Max
# 4
# 3
Model
Frequency
Operating
Frequency
Part Number
Stability1 Temperature (ºC) Range (MHz)
Number
3.4 Max
475B-Frequency-xxxxx
474B-Frequency-xxxxx
550B-Frequency-xxxxx
476B-Frequency-xxxxx
636B-Frequency-xxxxx
±100PPM
±100PPM
±50PPM
±50PPM
±25PPM
-40 ~ +85
-40 ~ +125
-40 ~ +85
-40 ~ +125
-40 ~ +85
2.000 ~ 135.000
2.000 ~ 48.000
2.000 ~ 135.000
2.000 ~ 48.000
2.000 ~ 135.000
FA530R
FA530
FA535R
FA535
# 2
# 1
FA536R
1.3 Max
• ELECTRICAL CHARACTERISTICS
MAX (unless otherwise noted)
PARAMETERS
2.54
Frequency Range (Fo)
Storage Temperature Range (Tstg)
see chart above
-55ºC ~ +150ºC
3.3V ±10%
# 2
# 1
Supply Voltage
Input Current
(Vdd)
(Idd)
# 3
1.0
# 4
1.2
2.000 ~ 19.999999 MHz
20.000 ~ 31.999999 MHz
32.000 ~ 49.999999 MHz
50.000 ~ 79.999999 MHz
80.000 ~ 99.999999 MHz
100.000 ~ 135.000 MHz
7mA
12mA
20mA
25mA
30mA
40mA
40% ~ 60%3
R e c om m e nde d
S olde r P a d L a y out
2.54
1.29
Output Symmetry (50% Vdd)
Rise/Fall Time (10% ~ 90% Vdd LeveLs)
2.000 ~ 49.999999 MHz
50.000 ~ 79.999999 MHz
80.000 ~ 99.999999 MHz
100.000 ~ 135.000 MHz
2.25
# 1
10nS
8nS
5nS
4nS
1.24
Output Voltage
(VoL)
(Voh)
(IoL)
(Ioh)
(HCMOS)
(Ist)
10% Vdd
90% Vdd Min
2mA Min
-2mA Min
15pF
10µA
10mS
100nS
10mS
P in C onne c tions
#1 E/D
#3 Output
#4 V DD
Output Current
#2 GꢀD
Output Load
Standby Current
Start-up Time
(Ts)
Output Disable Time 2
Output Enable Time 2
Aging (per year @25C)
Maximum Soldering Temp / Time
Moisture Sensitivity Level (MSL)
Termination Finish
±5 PPM
260ºC / 10 Seconds
1
• EꢀAbLE / DISAbLE FUꢀCTIOꢀ
(Pin 1)
OUTPUT (Pin 3)
ACTIVE
OPEN 2
Au
1 Inclusive of 25ºC tolerance, operating temperature range.
2 An internal pullup resistor from pin 1 to pin 4 allows active output if pin 1 is left open.
3 45/55 symmetry available on an inquiry basis.
'1' Level Vih ≥ 80% Vdd
'0' Level ViL ≤ 20% Vdd
ACTIVE
High Z
Notes: A 0.01µF bypass capacitor should be placed between Vdd (Pin 4) and GND (Pin 2) to
minimize power supply line noise.
Dimensional drawing is for reference to critical specifications defined by size measurements.
Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may
vary. All specifications subject to change without notice.
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