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F4605U PDF预览

F4605U

更新时间: 2024-11-07 01:23:23
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描述
LV-PECL 3.3V Oscillator

F4605U 数据手册

 浏览型号F4605U的Datasheet PDF文件第2页 
lV-PEcl 3.3V oꢀꢁꢂꢃꢃꢄꢅꢆr  
RꢆHs cꢆmpꢃꢂꢄꢇꢅ / Pꢉ Free / REacH cꢆmpꢃꢂꢄꢇꢅ  
F4600u sERiEs  
Rev. 5/23/2014  
Page 1 of 2  
http://www.foxonline.com/need_a_sample.htm  
FEatuREs  
3.3V Operation  
• -40 to +85ºC Operating Temperature  
LV-PECL Output  
• 7x5mm Ceramic Package  
• Low Phase Jitter (0.1pS RMS Max)  
• PaRt nuMbER sElEction  
7.2 Mꢄx  
Frequency  
Range (MHz)  
Operating  
Model Frequency  
Part Number  
#6 #5 #4  
Number Stability1 Temperature (ºC)  
0.207  
70.000 ~ 170.000  
70.000 ~ 170.000  
70.000 ~ 170.000  
70.000 ~ 170.000  
70.000 ~ 170.000  
70.000 ~ 170.000  
535U-Frequency-xxxxx  
536U-Frequency-xxxxx  
537U-Frequency-xxxxx  
538U-Frequency-xxxxx  
539U-Frequency-xxxxx  
540U-Frequency-xxxxx  
F4600U  
F4600RU ±100PPM  
±100PPM  
-10 ~ +70  
-40 ~ +85  
-10 ~ +70  
-40 ~ +85  
-10 ~ +70  
-40 ~ +85  
5.2 Mꢄx  
F4605U  
F4605RU  
F4606U  
±50PPM  
±50PPM  
±25PPM  
#1 #2 #3  
1.6 Mꢄx  
F4606RU ±25PPM  
• ElEctRical cHaRactERistics  
2.54  
1.4  
MAX (unless otherwise noted)  
PARAMETERS  
70.000 ~ 170.000 MHz  
-55ºC ~ +125ºC  
3.3V ± 5%  
Frequency Range (Fo)  
Storage Temperature Range (Tstg)  
#1 #2 #3  
#6 #5 #4  
2.6  
Supply Voltage  
Input Current  
(Vdd)  
(Idd)  
75mA  
5.08  
45% ~ 55%  
1nS  
1nS  
Output Symmetry (50% Vp-p)  
Rise Time (Tr) (20% ~ 80% Vp-p)  
Fall Time (Tf)(80% ~ 20% Vp-p)  
R e c om m e nde d  
S olde r P a d L a y out  
1.68V  
Output Voltage  
(Vol)  
(Voh)  
2.275V Min  
50 Ohms into Vdd -2.0 Vdc  
3mS  
0.1 pS RMS  
260ºC / 10 Seconds  
Au over Ni  
2.54 2.54  
Output Load  
Start-up Time  
Phase Jitter  
Maximum Soldering Temp / Time  
Termination Finish  
(Ts)  
2.0  
(12kHz to 20MHz)  
4.2  
#1  
1 Inclusive of 25ºC tolerance after reflow, operating temperature range, supply voltage change, and  
aging.  
2 An internal pullup resistor from pin 1 to pin 6 allows active output if pin 1 is left open.  
Notes:  
1.8  
*A 0.01µF capacitor should be placed between Vdd (Pin 6) and GND (Pin 3) to  
minimize power supply line noise.  
Pꢂꢇ cꢆꢇꢇeꢁꢅꢂꢆꢇꢀ  
*Dimensional drawing is for reference to critical specifications defined by size measurements.  
Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may vary.  
All specifications subject to change without notice.  
#1 E/D  
#2 nc*  
#3 GnD  
#4 oꢈꢅpꢈꢅ 1  
#5 oꢈꢅpꢈꢅ 2  
#6 VDD  
*nc ꢂꢀ nꢆ cꢆꢇꢇeꢁꢅ  
aꢃꢃ dꢂmeꢇꢀꢂꢆꢇꢀ ꢄre ꢂꢇ mꢂꢃꢃꢂmeꢅerꢀ.  
• EnablE / DisablE Function  
OUTPUT (Pin 4)  
ACTIVE  
OUTPUT (Pin 5)  
ACTIVE  
(Pin 1)  
OPEN2  
ACTIVE  
High Z  
ACTIVE  
High Z  
'1' Level Vih 70% Vdd  
'0' Level Vil 30% Vdd  
Fox Electronics  
5570 Enterprise Parkway  
Fort Myers, Florida 33905  
USA +1.239.693.0099  
FAX +1.239.693.1554  
An Integrated Device Technology, Inc. company  
FOXonline.com  

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