v4.3
eX Family FPGAs
FuseLock
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Live on Power-Up
No Power-Up/Down Sequence Required for Supply
Voltages
Leading Edge Performance
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240 MHz System Performance
350 MHz Internal Performance
3.9 ns Clock-to-Out (Pad-to-Pad)
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Configurable Weak-Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
Individual Output Slew Rate Control
2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation
with 5.0V Input Tolerance and 5.0V Drive Strength
Software Design Support with Actel Designer and
Libero™ Integrated Design Environment (IDE)
Tools
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Specifications
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3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22µm CMOS Process Technology
Up to 132 User-Programmable I/O Pins
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Up to 100% Resource Utilization with 100% Pin
Locking
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Deterministic Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Fuselock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Features
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High-Performance, Low-Power Antifuse FPGA
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LP/Sleep Mode for Additional Power Savings
Advanced Small-Footprint Packages
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
Product Profile
Device
eX64
eX128
eX256
Capacity
3,000
2,000
6,000
4,000
12,000
8,000
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64
128
128
256
256
512
Combinatorial Cells
Maximum User I/Os
128
84
256
100
512
132
Global Clocks
Hardwired
Routed
1
2
1
2
1
2
Speed Grades
–F, Std, –P
C, I, A
–F, Std, –P
C, I, A
–F, Std, –P
C, I, A
Temperature Grades*
Package (by pin count)
TQFP
CSP
64, 100
49, 128
64, 100
49, 128
100
128, 180
Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.
June 2006
i
© 2006 Actel Corporation