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EVAL-AD7768-4FMCZ PDF预览

EVAL-AD7768-4FMCZ

更新时间: 2024-11-25 01:11:43
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
99页 2306K
描述
8-/4-Channel, 24-Bit, Simultaneous Sampling ADCs with Power Scaling, 110.8 kHz BW

EVAL-AD7768-4FMCZ 数据手册

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8-/4-Channel, 24-Bit, Simultaneous Sampling  
ADCs with Power Scaling, 110.8 kHz BW  
Data Sheet  
AD7768/AD7768-4  
Low latency sinc5 filter  
FEATURES  
Wideband brick wall filter: 0.005 dB pass-band ripple  
from dc to 102.4 kHz  
Analog input precharge buffers  
Precision ac and dc performance  
8-/4-channel simultaneous sampling  
256 kSPS maximum ADC output data rate per channel  
108 dB dynamic range  
Power supply  
AVDD1 = 5.0 V, AVDD2 = 2.25 V to 5.0 V  
IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V  
64-lead LQFP package, no exposed pad  
Temperature range: −40°C to +105°C  
110.8 kHz maximum input bandwidth (−3 dB bandwidth)  
−120 dB total harmonic distortion (THD) typical  
2 ppm of full-scale range (FSR) integral nonlinearity  
(INL), 50 µV offset error, 30 ppm gain error  
Optimized power dissipation vs. noise vs. input bandwidth  
Selectable power, speed, and input bandwidth (BW) modes  
Fast: highest speed; 110.8 kHz BW, 51.5 mW per channel  
Median: half speed, 55.4 kHz BW, 27.5 mW per channel  
Eco: lowest power, 13.8 kHz BW, 9.375 mW per channel  
Input BW range: dc to 110.8 kHz  
APPLICATIONS  
Data acquisition systems: USB/PXI/Ethernet  
Instrumentation and industrial control loops  
Audio test and measurement  
Vibration and asset condition monitoring  
3-phase power quality analysis  
Programmable input bandwidth/sampling rates  
Cyclic redundancy check (CRC) error checking on data interface  
Daisy-chaining  
Sonar  
High precision medical electroencephalogram (EEG)/  
electromyography (EMG)/electrocardiogram (ECG)  
Linear phase digital filter  
FUNCTIONAL BLOCK DIAGRAM  
AVDD1A,  
AVDD1B  
AVDD2A, REGCAPA,  
REFx+ REFx–  
AVDD2B REGCAPB DGND  
IOVDD  
DREGCAP  
BUFFERED  
VCM  
1.8V  
LDO  
1.8V  
LDO  
PRECHARGE  
REFERENCE  
BUFFERS  
VCM  
×8  
VCM  
SYNC_IN  
SYNC_OUT  
START  
AIN0+  
AIN0–  
AIN1+  
AIN1–  
P
P
P
P
P
P
OFFSET,  
Σ-Δ  
RESET  
DIGITAL  
FILTER  
ENGINE  
CH 0  
GAIN PHASE  
CORRECTION  
ADC  
FORMAT1*  
FORMAT0  
OFFSET,  
GAIN PHASE  
CORRECTION  
Σ-Δ  
ADC  
CH 1  
ADC  
OUTPUT  
DATA  
DRDY  
SINC5  
LOW LATENCY  
FILTER  
AIN2+  
AIN2–  
DCLK  
SERIAL  
OFFSET,  
GAIN PHASE  
CORRECTION  
Σ-Δ  
ADC  
CH 2  
INTERFACE  
DOUT0  
DOUT1  
DOUT2  
DOUT3  
DOUT4*  
DOUT5*  
DOUT6*, DIN  
DOUT7*  
AIN3+  
AIN3–  
AIN4+  
AIN4–  
P
P
OFFSET,  
GAIN PHASE  
CORRECTION  
Σ-Δ  
ADC  
CH 3  
CH 4*  
CH 5*  
WIDEBAND  
LOW RIPPLE  
FILTER  
P
P
OFFSET,  
GAIN PHASE  
CORRECTION  
Σ-Δ  
ADC  
AIN5+  
AIN5–  
P
P
OFFSET,  
GAIN PHASE  
CORRECTION  
Σ-Δ  
ADC  
ST0/CS  
SPI  
ST1*/SCLK  
DEC0/SDO  
DEC1/SDI  
CONTROL  
INTERFACE  
P
P
AIN6+  
AIN6–  
OFFSET,  
Σ-Δ  
CH 6*  
CH 7*  
GAIN PHASE  
CORRECTION  
ADC  
AIN7+  
AIN7–  
P
P
OFFSET,  
GAIN PHASE  
CORRECTION  
Σ-Δ  
ADC  
PIN/SPI  
×16 ANALOG INPUT  
PRECHARGE BUFFERS (P)  
AD7768/AD7768-4  
AVSS  
XTAL2/MCLK XTAL1  
MODE3/GPIO3 FILTER/GPIO4  
TO  
*THESE CHANNELS/PINS EXIST ONLY ON THE AD7768.  
MODE0/GPIO0  
Figure 1.  
Rev. A  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2016 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 

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