3-Channel, Low Noise, Low Power, 20-Bit ∑-Δ
ADC with On-Chip In-Amp and Reference
AD7785
Industrial process control
FEATURES
Instrumentation
Portable instrumentation
Blood analysis
Smart transmitters
Liquid/gas chromatography
6-digit DVM
Up to 20 bits effective resolution
RMS noise
40 nV @ 4.17 Hz
85 nV @ 16.7 Hz
Current: 400 μA typical
Power-down: 1 μA maximum
Low noise programmable gain instrumentation amp
Band gap reference with 4 ppm/°C drift typical
Update rate: 4.17 Hz to 470 Hz
3 differential inputs
GENERAL DESCRIPTION
The AD7785 is a low power, low noise, complete analog front
end for high precision measurement applications. The AD7785
contains a low noise 20-bit ∑-Δ ADC with three differential
analog inputs. The on-chip, low noise instrumentation amplifier
means that signals of small amplitude can be interfaced directly
to the ADC. With a gain setting of 64, the rms noise is 40 nV
when the update rate equals 4.17 Hz.
Internal clock oscillator
Simultaneous 50 Hz/60 Hz rejection
Programmable current sources
On-chip bias voltage generator
Burnout currents
The device contains a precision low noise, low drift internal
band gap reference and can accept an external differential
reference. Other on-chip features include programmable
excitation current sources, burnout currents, and a bias voltage
generator. The bias voltage generator sets the common-mode
voltage of a channel to AVDD/2.
Power supply: 2.7 V to 5.25 V
–40°C to +105°C temperature range
Independent interface power supply
16-lead TSSOP package
Interface
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
The AD7785 can be operated with either the internal clock
or an external clock. The output data rate from the device is
software-programmable and can be varied from 4.17 Hz to 470
Hz. The device operates with a power supply from 2.7 V to
5.25 V. It consumes a current of 400 μA typical and is housed in
a 16-lead TSSOP package.
APPLICATIONS
Thermocouple measurements
RTD measurements
Thermistor measurements
Gas analysis
FUNCTIONAL BLOCK DIAGRAM
DD
GND
AV
REFIN(+)/AIN3(+) REFIN(–)/AIN3(–)
V
BIAS
BAND GAP
REFERENCE
GND
AV
DD
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
DOUT/RDY
DIN
SERIAL
INTERFACE
AND
CONTROL
LOGIC
MUX
Σ-Δ
ADC
BUF
IN-AMP
SCLK
CS
AV
DD
GND
DV
DD
IOUT1
IOUT2
INTERNAL
CLOCK
AD7785
CLK
Figure 1.
Rev. 0
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