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EPM7032AELC44-10N PDF预览

EPM7032AELC44-10N

更新时间: 2024-11-06 13:37:59
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟LTEPC输入元件可编程逻辑
页数 文件大小 规格书
64页 436K
描述
EE PLD, 10ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44

EPM7032AELC44-10N 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Transferred零件包装代码:LCC
包装说明:PLASTIC, LCC-44针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.14
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:1582497Samacsys Pin Count:44
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Plastic Leaded Chip Carrier
Samacsys Footprint Name:(44-Pin) J-LEAD Chip Carrier PLCCSamacsys Released Date:2020-02-22 05:02:38
Is Samacsys:N其他特性:32 MACROCELLS; 2 LABS; CONFIGURABLE I/O OPERATION WITH 2.5 OR 3.3
最大时钟频率:103.1 MHz系统内可编程:YES
JESD-30 代码:S-PQCC-J44JESD-609代码:e3
JTAG BST:YES长度:16.5862 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:36宏单元数:32
端子数量:44最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 36 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245电源:2.5/3.3,3.3 V
可编程逻辑类型:EE PLD传播延迟:10 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Programmable Logic Devices最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:16.5862 mmBase Number Matches:1

EPM7032AELC44-10N 数据手册

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MAX 7000A  
Programmable Logic  
Device  
Includes  
MAX 7000AE  
®
September 2003, ver. 4.5  
Data Sheet  
High-performance 3.3-V EEPROM-based programmable logic  
devices (PLDs) built on second-generation Multiple Array MatriX  
(MAX®) architecture (see Table 1)  
3.3-V in-system programmability (ISP) through the built-in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with  
advanced pin-locking capability  
Features...  
MAX 7000AE device in-system programmability (ISP) circuitry  
compliant with IEEE Std. 1532  
EPM7128A and EPM7256A device ISP circuitry compatible with  
IEEE Std. 1532  
Built-in boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1  
Supports JEDEC Jam Standard Test and Programming Language  
(STAPL) JESD-71  
Enhanced ISP features  
Enhanced ISP algorithm for faster programming (excluding  
EPM7128A and EPM7256A devices)  
ISP_Done bit to ensure complete programming (excluding  
EPM7128A and EPM7256A devices)  
Pull-up resistor on I/O pins during in-system programming  
Pin-compatible with the popular 5.0-V MAX 7000S devices  
High-density PLDs ranging from 600 to 10,000 usable gates  
Extended temperature range  
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V  
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.  
f
Altera Corporation  
1
DS-M7000A-4.5  

EPM7032AELC44-10N 替代型号

型号 品牌 替代类型 描述 数据表
EPM7032AELC44-7N ALTERA

完全替代

EE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
EPM7032AELC44-10 ALTERA

完全替代

EE PLD, 10ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
EPM3032ALC44-10N ALTERA

类似代替

Programmable Logic Device Family

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