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EPM5128LC68-2 PDF预览

EPM5128LC68-2

更新时间: 2024-01-02 18:06:15
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟输入元件可编程逻辑
页数 文件大小 规格书
34页 649K
描述
OT PLD, 45ns, CMOS, PQCC68, PLASTIC, LCC-68

EPM5128LC68-2 数据手册

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MAX 5000  
Programmable Logic  
Device Family  
®
May 1999, ver. 5  
Data Sheet  
Advanced Multiple Array MatriX (MAX®) 5000 architecture  
combining speed and ease-of-use of PAL devices with the density of  
programmable gate arrays  
Complete family of high-performance, erasable CMOS EPROM  
erasable programmable logic devices (EPLDs) for designs ranging  
from fast 28-pin address decoders to 100-pin LSI custom peripherals  
600 to 3,750 usable gates (see Table 1)  
Fast, 15-ns combinatorial delays and 76.9-MHz counter frequencies  
Configurable expander product-term distribution allowing more  
than 32 product terms in a single macrocell  
Features...  
28 to 100 pins available in dual in-line package (DIP), J-lead chip  
carrier, pin-grid array (PGA), and quad flat pack (QFP) packages  
Programmable registers providing D, T, JK, and SR flipflop  
functionality with individual clear, preset, and clock controls  
Programmable security bit for protection of proprietary designs  
Software design support featuring the Altera® MAX+PLUS® II  
development system on Windows-based PCs, as well as  
Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC  
System/6000 workstations  
Table 1. MAX 5000 Device Features  
Feature EPM5032  
9
EPM5064  
EPM5128  
EPM5130  
EPM5192  
Usable gates  
600  
32  
1,250  
64  
2,500  
128  
8
2,500  
128  
8
3,750  
192  
12  
Macrocells  
Logic array blocks (LABs)  
Expanders  
1
4
64  
128  
PIA  
36  
256  
PIA  
60  
256  
PIA  
84  
384  
PIA  
72  
Routing  
Global  
24  
Maximum user I/O pins  
t
t
t
f
(ns)  
15  
25  
25  
25  
25  
PD  
(ns)  
4
4
4
4
4
ASU  
(ns)  
10  
14  
14  
14  
14  
CO  
(MHz)  
76.9  
50  
50  
50  
50  
CNT  
Altera Corporation  
709  
A-DS-M5000-05  

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