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EPM1270T144C3N PDF预览

EPM1270T144C3N

更新时间: 2024-01-25 04:52:05
品牌 Logo 应用领域
英特尔 - INTEL 输入元件可编程逻辑
页数 文件大小 规格书
88页 982K
描述
Flash PLD, 6.2ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144

EPM1270T144C3N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFP
包装说明:22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144针数:144
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.39.00.01风险等级:3.34
其他特性:IT CAN ALSO OPERATE AT 3.3V系统内可编程:YES
JESD-30 代码:S-PQFP-G144JESD-609代码:e3
JTAG BST:YES长度:20 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:116宏单元数:980
端子数量:144最高工作温度:85 °C
最低工作温度:组织:0 DEDICATED INPUTS, 116 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP144,.87SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.5/3.3,2.5/3.3 V
可编程逻辑类型:FLASH PLD传播延迟:6.2 ns
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Programmable Logic Devices最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:20 mmBase Number Matches:1

EPM1270T144C3N 数据手册

 浏览型号EPM1270T144C3N的Datasheet PDF文件第82页浏览型号EPM1270T144C3N的Datasheet PDF文件第83页浏览型号EPM1270T144C3N的Datasheet PDF文件第84页浏览型号EPM1270T144C3N的Datasheet PDF文件第86页浏览型号EPM1270T144C3N的Datasheet PDF文件第87页浏览型号EPM1270T144C3N的Datasheet PDF文件第88页 
Chapter 5: DC and Switching Characteristics  
5–27  
Document Revision History  
Document Revision History  
Table 5–35 shows the revision history for this chapter.  
Table 5–35. Document Revision History (Part 1 of 2)  
Date and Revision  
Changes Made  
Summary of Changes  
August 2009,  
version 2.5  
Added Table 5–28, Table 5–29, and Table 5–30.  
Added information for  
speed grade –8  
Updated Table 5–2, Table 5–4, Table 5–14, Table 5–15, Table 5–16,  
Table 5–17, Table 5–18, Table 5–19, Table 5–20, Table 5–21,  
Table 5–22, Table 5–23, Table 5–24, Table 5–27, Table 5–31,  
Table 5–32, and Table 5–33.  
November 2008,  
version 2.4  
Updated Table 5–2.  
Updated “Internal Timing Parameters” section.  
Updated New Document Format.  
UpdatedFigure 5–1.  
October 2008,  
version 2.3  
July 2008,  
version 2.2  
Updated Table 5–14 , Table 5–23 , and Table 5–24.  
March 2008,  
version 2.1  
Added (Note 5) to Table 5–4.  
December 2007,  
version 2.0  
Updated (Note 3) and (4) to Table 5–1.  
Updated Table 5–2 and added (Note 5).  
Updated document with  
MAX IIZ information.  
Updated ICCSTANDBY and ICCPOWERUP information and added  
IPULLUP information in Table 5–4.  
Added (Note 1) to Table 5–10.  
Updated Figure 5–2.  
Added (Note 1) to Table 5–13.  
Updated Table 5–13 through Table 5–24, and Table 5–27 through  
Table 5–30.  
Added tCOMB information to Table 5–15.  
Updated Figure 5–6.  
Added “Referenced Documents” section.  
Added note to Table 5–1.  
December 2006,  
version 1.8  
Added document revision history.  
Minor content and table updates.  
July 2006,  
version 1.7  
February 2006,  
version 1.6  
Updated “External Timing I/O Delay Adders” section.  
Updated Table 5–29.  
Updated Table 5–30.  
November 2005,  
version 1.5  
Updated Tables 5-2, 5-4, and 5-12.  
August 2005,  
version 1.4  
Updated Figure 5-1.  
Updated Tables 5-13, 5-16, and 5-26.  
Removed Note 1 from Table 5-12.  
© August 2009 Altera Corporation  
MAX II Device Handbook  

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EPM1270T144C5N ALTERA Flash PLD, 10ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144

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