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EPF10K30EFI484-3DX PDF预览

EPF10K30EFI484-3DX

更新时间: 2024-11-06 23:51:11
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其他 - ETC /
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120页 1759K
描述
ASIC

EPF10K30EFI484-3DX 数据手册

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FLEX 10KE  
Embedded Programmable  
Logic Family  
®
September 2000, ver. 2.10  
Data Sheet  
 
Embedded programmable logic devices (PLDs), providing  
system-on-a-programmable-chip integration in a single device  
Features...  
Enhanced embedded array for implementing megafunctions  
such as efficient memory and specialized logic functions  
Dual-port capability with up to 16-bit width per embedded array  
block (EAB)  
Logic array for general logic functions  
 
 
High density  
30,000 to 200,000 typical gates (see Tables 1 and 2)  
Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be  
used without reducing logic capacity  
System-level features  
MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or  
5.0-V devices  
Low power consumption  
Bidirectional I/O performance (t and t ) up to 212 MHz  
Fully compliant with the PCI Special Interest Group (PCI SIG)  
PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at  
33 MHz or 66 MHz  
SU  
CO  
-1 speed grade devices are compliant with PCI Local Bus  
Specification, Revision 2.2, for 5.0-V operation  
Built-in Joint Test Action Group (JTAG) boundary-scan test  
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available  
without consuming additional device logic  
For information on 5.0-V FLEX® 10K or 3.3-V FLEX 10KA devices, see the  
FLEX 10K Embedded Programmable Logic Family Data Sheet.  
f
Table 1. FLEX 10KE Device Features  
Feature  
EPF10K30E  
EPF10K50E  
EPF10K50S  
EPF10K100B  
Typical gates (1)  
Maximum system gates  
Logic elements (LEs)  
EABs  
30,000  
119,000  
1,728  
6
50,000  
199,000  
2,880  
10  
100,000  
158,000  
4,992  
12  
Total RAM bits  
24,576  
220  
40,960  
254  
24,576  
191  
Maximum user I/O pins  
Altera Corporation  
1
A-DS-F10KE-02.10  

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