Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
In addition to transmitting configuration data to the FPGAs, the
configuration circuit is also responsible for pausing configuration
whenever there is insufficient data available for transmission. This occurs
when the flash read bandwidth is lower than the configuration write
bandwidth. Configuration is paused by stopping the DCLKto the FPGA,
when waiting for data to be read from the flash or for data to be
decompressed. This technique is called “Pausing DCLK.”
The enhanced configuration device flash memories feature a 90-ns access
time (approximately 10 MHz). Hence, the flash read bandwidth is limited
to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at
10 MHz). However, the configuration speeds supported by Altera FPGAs
are much higher and translate to high configuration write bandwidths.
For instance, 100-MHz Stratix FPP configuration requires data at the rate
of 800 Mbps (8-bit DATA[]bus at 100 MHz). This is much higher than the
160 Mbps the flash memory can support, and is the limiting factor for
configuration time. Compression increases the effective flash read
bandwidth since the same amount of configuration data takes up less
space in the flash memory after compression. Since Stratix configuration
data compression ratios are approximately two, the effective read
bandwidth doubles to about 320 Mbps.
Finally, the configuration controller also manages errors during
configuration. A CONF_DONEerror occurs when the FPGA does not de-
assert its CONF_DONEsignal within 64 DCLK cycles after the last bit of
configuration data is transmitted. When a CONF_DONEerror is detected,
the controller pulses the OEline low, which pulls nSTATUSlow and
triggers another configuration cycle.
A cyclic redundancy check (CRC) error occurs when the FPGA detects
corruption in the configuration data. This corruption could be a result of
noise coupling on the board such as poor signal integrity on the
configuration signals. When this error is signaled by the FPGA (by
driving the nSTATUSline low), the controller stops configuration. If the
Auto-Restart Configuration After Error option is enabled in the FPGA,
it releases its nSTATUSsignal after a reset time-out period and the
controller attempts to reconfigure the FPGA.
After the FPGA configuration process is complete, the controller drives
DCLKlow and the DATA[]pins high. Additionally, the controller tri-
states its internal interface to the flash memory, enables the weak internal
pull-ups on the flash address and control lines, and enables bus-keep
circuits on flash data lines.
The following sections briefly describe the different configuration
schemes supported by the enhanced configuration device: FPP, PS, and
concurrent configuration.
Altera Corporation
August 2005
2–5
Configuration Handbook, Volume 2
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