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EP3CLS200F780C7N PDF预览

EP3CLS200F780C7N

更新时间: 2024-02-02 11:08:27
品牌 Logo 应用领域
英特尔 - INTEL 时钟可编程逻辑
页数 文件大小 规格书
32页 760K
描述
Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE, FBGA-780

EP3CLS200F780C7N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:LEAD FREE, FBGA-780针数:780
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.39.00.01风险等级:5.24
最大时钟频率:450 MHzJESD-30 代码:S-PBGA-B780
JESD-609代码:e1长度:29 mm
湿度敏感等级:3可配置逻辑块数量:198464
输入次数:413逻辑单元数量:198464
输出次数:413端子数量:780
最高工作温度:85 °C最低工作温度:
组织:198464 CLBS封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA780,28X28,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):245电源:1.2,1.2/3.3,2.5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:2.4 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.25 V最小供电电压:1.15 V
标称供电电压:1.2 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:29 mm
Base Number Matches:1

EP3CLS200F780C7N 数据手册

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2–4  
Chapter 2: Cyclone III LS Device Datasheet  
Electrical Characteristics  
Recommended Operating Conditions  
This section lists the functional operation limits for AC and DC parameters for  
Cyclone III LS devices.  
The steady-state voltage and current values expected from Cyclone III LS devices are  
provided in Table 2–3. All supplies must be strictly monotonic without plateaus.  
Table 2–3. Cyclone III LS Devices Recommended Operating Conditions (1), (2)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
(3)  
VCCINT  
Supply voltage for internal logic  
1.15  
1.2  
1.25  
V
Supply voltage for output buffers, 3.3-V  
operation  
3.135  
2.85  
3.3  
3.0  
2.5  
1.8  
1.5  
1.2  
3.465  
3.15  
V
V
V
V
V
V
Supply voltage for output buffers, 3.0-V  
operation  
Supply voltage for output buffers, 2.5-V  
operation  
2.375  
1.71  
2.625  
1.89  
(3), (7)  
VCCIO  
Supply voltage for output buffers, 1.8-V  
operation  
Supply voltage for output buffers, 1.5-V  
operation  
1.425  
1.14  
1.575  
1.26  
Supply voltage for output buffers, 1.2-V  
operation  
(3)  
VCCA  
Supply (analog) voltage for PLL regulator  
Supply (digital) voltage for PLL  
2.375  
1.15  
2.5  
1.2  
2.625  
1.25  
V
V
(3)  
VCCD_PLL  
Battery back-up power supply for design  
security volatile key register  
(4)  
VCCBAT  
1.2  
3.0  
3.3  
V
VI  
Input voltage  
–0.5  
0
3.6  
VCCIO  
85  
V
VO  
Output voltage  
V
For commercial use  
0
°C  
°C  
TJ  
Operating junction temperature  
Power supply ramptime  
For industrial use  
–40  
50 µs  
50 µs  
100  
(5)  
Standard POR  
50 ms  
3 ms  
tRAMP  
IDiode  
(6)  
Fast POR  
Magnitude of DC current across  
PCI-clamp diode when enabled  
10  
mA  
Notes to Table 2–3:  
(1) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when you do not use phase  
locked-loops [PLLs}), and must be powered up and powered down at the same time.  
(2) VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead.  
(3) VCC must rise monotonically.  
(4) VCCBAT is tied to POR. If the VCCBAT is below 1.2 V, the device will not power up.  
(5) POR time for Standard POR ranges from 50 to 200 ms. Each individual power supply must reach the recommended operating range within  
50 ms.  
(6) POR time for Fast POR ranges from 3 to 9 ms. Each individual power supply must reach the recommended operating range within 3 ms.  
(7) All input buffers are powered by the VCCIO supply.  
DC Characteristics  
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)  
tolerance, and bus hold specifications for Cyclone III LS devices.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  

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