Datasheet > EP3CLS100U484C8N

EP3CLS100U484C8N

更新时间： 2024-01-12 18:26:18

品牌	Logo	应用领域
英特尔 - INTEL		时钟 LTE 栅可编程逻辑
页数	文件大小	规格书
32页	760K
描述
Field Programmable Gate Array, 100448 CLBs, 450MHz, 100448-Cell, CMOS, PBGA484, LEAD FREE, UBGA-484

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EP3CLS100U484C8N 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LEAD FREE, UBGA-484	针数：	484
Reach Compliance Code：	unknown	ECCN代码：	3A991
HTS代码：	8542.39.00.01	风险等级：	5.28
最大时钟频率：	450 MHz	JESD-30 代码：	S-PBGA-B484
JESD-609代码：	e1	长度：	19 mm
湿度敏感等级：	3	可配置逻辑块数量：	100448
输入次数：	278	逻辑单元数量：	100448
输出次数：	278	端子数量：	484
最高工作温度：	85 °C	最低工作温度：
组织：	100448 CLBS	封装主体材料：	PLASTIC/EPOXY
封装代码：	FBGA	封装等效代码：	BGA484,22X22,32
封装形状：	SQUARE	封装形式：	GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	1.2,1.2/3.3,2.5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.05 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.25 V	最小供电电压：	1.15 V
标称供电电压：	1.2 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	0.5 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	19 mm
Base Number Matches：	1

EP3CLS100U484C8N 数据手册

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Chapter 2: Cyclone III LS Device Datasheet

2–31

Glossary

Table 2–39. Glossary (Part 6 of 6)

Letter

Term

V_CM(DC)

Definitions

DC common mode input voltage.

AC differential Input Voltage—The minimum AC input differential voltage required for

switching.

V_DIF(AC)

DC differential Input Voltage—The minimum DC input differential voltage required for

switching.

V_DIF(DC)

V_ICM

Input Common Mode Voltage—The common mode of the differential signal at the receiver.

Input differential Voltage Swing—The difference in voltage between the positive and

complementary conductors of a differential transmission at the receiver.

V_ID

Voltage Input High—The minimum positive voltage applied to the input that is accepted by

the device as a logic high.

V_IH

V_IH(AC)

V_IH(DC)

High-level AC input voltage.

High-level DC input voltage.

Voltage Input Low—The maximum positive voltage applied to the input that is accepted by

the device as a logic low.

V_IL

V_{IL (AC)}

V_{IL (DC)}

V_IN

Low-level AC input voltage.

Low-level DC input voltage.

DC input voltage.

Output Common Mode Voltage—The common mode of the differential signal at the

transmitter.

V_OCM

V_OD

Output differential Voltage Swing—The difference in voltage between the positive and

complementary conductors of a differential transmission at the transmitter. V_OD= V_OH– V_OL.

Voltage Output High—The maximum positive voltage from an output that the device

considers will be accepted as the minimum positive high level.

V_OH

Voltage Output Low—The maximum positive voltage from an output that the device considers

will be accepted as the maximum positive low level.

V_OL

V_OS

Output offset voltage—V_OS= (V_OH+ V_OL) / 2.

AC differential Output cross point voltage—The voltage at which the differential output signals

must cross.

V_{OX (AC)}

V_REF

Reference voltage for the SSTL and HSTL I/O standards.

AC input reference voltage for the SSTL and HSTL I/O standards. V_REF(AC)= V_REF(DC)+ noise.

V_{REF (AC)}

V_{REF (DC)}

V_{SWING (AC)}

The peak-to-peak AC noise on V_REFmust not exceed 2% of V_REF(DC)

DC input reference voltage for the SSTL and HSTL I/O standards.

AC differential Input Voltage—AC Input differential voltage required for switching. Refer to

Input Waveforms for the SSTL Differential I/O Standard.

DC differential Input Voltage—DC Input differential voltage required for switching. Refer to

Input Waveforms for the SSTL Differential I/O Standard.

V_{SWING (DC)}

V_TT

Termination voltage for the SSTL and HSTL I/O standards.

AC differential Input cross point Voltage—The voltage at which the differential input signals

must cross.

V_{X (AC)}

—

July 2012 Altera Corporation

Cyclone III Device Handbook

Volume 2

1...28 29 303132

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与EP3CLS100U484C8N相关器件

型号	品牌	描述	获取价格	数据表
EP3CLS100U484I7N	INTEL	Field Programmable Gate Array, 100448 CLBs, 450MHz, 100448-Cell, CMOS, PBGA484, LEAD FREE,	获取价格
EP3CLS150	ALTERA	This section provides a complete overview of all features relating to the Cyclone III devi	获取价格
EP3CLS150F484C8N	INTEL	Field Programmable Gate Array, 150848 CLBs, 450MHz, 150848-Cell, CMOS, PBGA484, LEAD FREE,	获取价格
EP3CLS150F484I7	INTEL	Field Programmable Gate Array, 150848 CLBs, 450MHz, 150848-Cell, CMOS, PBGA484, 23 X 23 MM	获取价格
EP3CLS150F484I7N	INTEL	Field Programmable Gate Array, 150848 CLBs, 450MHz, 150848-Cell, CMOS, PBGA484, LEAD FREE,	获取价格
EP3CLS150F780C7N	INTEL	Field Programmable Gate Array, 150848 CLBs, 450MHz, 150848-Cell, CMOS, PBGA780, LEAD FREE,	获取价格

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