Datasheet > EP3CLS100U484C8N

EP3CLS100U484C8N

更新时间： 2024-01-23 00:06:29

品牌	Logo	应用领域
英特尔 - INTEL		时钟 LTE 栅可编程逻辑
页数	文件大小	规格书
32页	760K
描述
Field Programmable Gate Array, 100448 CLBs, 450MHz, 100448-Cell, CMOS, PBGA484, LEAD FREE, UBGA-484

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

EP3CLS100U484C8N 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LEAD FREE, UBGA-484	针数：	484
Reach Compliance Code：	unknown	ECCN代码：	3A991
HTS代码：	8542.39.00.01	风险等级：	5.28
最大时钟频率：	450 MHz	JESD-30 代码：	S-PBGA-B484
JESD-609代码：	e1	长度：	19 mm
湿度敏感等级：	3	可配置逻辑块数量：	100448
输入次数：	278	逻辑单元数量：	100448
输出次数：	278	端子数量：	484
最高工作温度：	85 °C	最低工作温度：
组织：	100448 CLBS	封装主体材料：	PLASTIC/EPOXY
封装代码：	FBGA	封装等效代码：	BGA484,22X22,32
封装形状：	SQUARE	封装形式：	GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	1.2,1.2/3.3,2.5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.05 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.25 V	最小供电电压：	1.15 V
标称供电电压：	1.2 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	0.5 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	19 mm
Base Number Matches：	1

EP3CLS100U484C8N 数据手册

浏览型号EP3CLS100U484C8N的Datasheet PDF文件第26页

浏览型号EP3CLS100U484C8N的Datasheet PDF文件第27页

浏览型号EP3CLS100U484C8N的Datasheet PDF文件第28页

浏览型号EP3CLS100U484C8N的Datasheet PDF文件第30页

浏览型号EP3CLS100U484C8N的Datasheet PDF文件第31页

浏览型号EP3CLS100U484C8N的Datasheet PDF文件第32页

Chapter 2: Cyclone III LS Device Datasheet

2–29

Glossary

Table 2–39. Glossary (Part 4 of 6)

Letter

Term

Definitions

V_CCIO

V_OH

V_{IH AC}

(

)

V_IH(DC)

V_REF

V_IL(DC)

V_IL(AC

)

Single-ended

Voltage

referenced I/O

Standard

V_OL

V_SS

The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal

values.

■ The AC values indicate the voltage levels at which the receiver must meet its timing

specifications.

■ The DC values indicate the voltage levels at which the final logic state of the receiver is

unambiguously defined.

After the receiver input crosses the AC value, the receiver changes to the new logic state. The

new logic state is then maintained as long as the input stays beyond the DC threshold. This

approach is intended to provide predictable receiver timing in the presence of input waveform

ringing.

High-speed I/O Block: The period of time during which the data must be valid to capture it

correctly. The setup and hold times determine the ideal strobe position in the sampling

window.

SW (Sampling

Window)

t_C

High-speed receiver and transmitter input and output clock period.

TCCS (Channel-

High-speed I/O Block: The timing difference between the fastest and slowest output edges,

to-channel-skew) including t_COvariation and clock skew. The clock is included in the TCCS measurement.

tcin

t_CO

Delay from the clock pad to the I/O input register.

Delay from the clock pad to the I/O output.

tcout

t_DUTY

t_FALL

t_H

Delay from the clock pad to the I/O output register.

High-speed I/O Block: Duty cycle on the high-speed transmitter output clock.

Signal high-to-low transition time (80 to 20%).

Input register hold time.

Timing Unit

Interval (TUI)

High-speed I/O block: The timing budget allowed for skew, propagation delays, and the data

sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w).

t_INJITTER

Period jitter on the PLL clock input.

t_{OUTJITTER_DEDCLK}

t_{OUTJITTER_IO}

tpllcin

Period jitter on the dedicated clock output driven by a PLL.

Period jitter on the general purpose I/O driven by a PLL.

Delay from the PLL inclk pad to the I/O input register.

Delay from the PLL inclk pad to the I/O output register.

tpllcout

July 2012 Altera Corporation

Cyclone III Device Handbook

Volume 2

1...26 27 282930 31 32

下载PDF

与EP3CLS100U484C8N相关器件

型号	品牌	描述	获取价格	数据表
EP3CLS100U484I7N	INTEL	Field Programmable Gate Array, 100448 CLBs, 450MHz, 100448-Cell, CMOS, PBGA484, LEAD FREE,	获取价格
EP3CLS150	ALTERA	This section provides a complete overview of all features relating to the Cyclone III devi	获取价格
EP3CLS150F484C8N	INTEL	Field Programmable Gate Array, 150848 CLBs, 450MHz, 150848-Cell, CMOS, PBGA484, LEAD FREE,	获取价格
EP3CLS150F484I7	INTEL	Field Programmable Gate Array, 150848 CLBs, 450MHz, 150848-Cell, CMOS, PBGA484, 23 X 23 MM	获取价格
EP3CLS150F484I7N	INTEL	Field Programmable Gate Array, 150848 CLBs, 450MHz, 150848-Cell, CMOS, PBGA484, LEAD FREE,	获取价格
EP3CLS150F780C7N	INTEL	Field Programmable Gate Array, 150848 CLBs, 450MHz, 150848-Cell, CMOS, PBGA780, LEAD FREE,	获取价格

与EP3CLS100U484C8N相关文章

SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
2024-05-23

5
AT89C51单片机资料手册详细解析及应用示例
2024-05-23

8
CP2102资料手册解读：CP2102引脚说明、关键参数分析
2024-05-23

4
资料手册解读：UC3842参数和管脚说明
2024-05-22

6

产品中心

服务支持

精选活动

关于我们

帮助中心

EP3CLS100U484C8N

EP3CLS100U484C8N 技术参数

EP3CLS100U484C8N 数据手册

与EP3CLS100U484C8N相关器件

与EP3CLS100U484C8N相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

EP3CLS100U484C8N

EP3CLS100U484C8N 技术参数

EP3CLS100U484C8N 数据手册

与EP3CLS100U484C8N相关器件

与EP3CLS100U484C8N相关文章

您还可以找

您在本页遇到什么问题？