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EP2C20Q208C6 PDF预览

EP2C20Q208C6

更新时间: 2023-02-15 00:00:00
品牌 Logo 应用领域
阿尔特拉 - ALTERA
页数 文件大小 规格书
399页 2564K
描述
Field Programmable Gate Array, 1196 CLBs, CMOS, PQFP208, PLASTIC, QFP-208

EP2C20Q208C6 数据手册

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Contents  
Cyclone II Device Handbook, Volume 1  
External Memory Interfacing ....................................................................................................... 2–44  
Programmable Drive Strength ..................................................................................................... 2–49  
Open-Drain Output ........................................................................................................................ 2–51  
Slew Rate Control ........................................................................................................................... 2–51  
Bus Hold .......................................................................................................................................... 2–51  
Programmable Pull-Up Resistor .................................................................................................. 2–52  
Advanced I/O Standard Support ................................................................................................ 2–52  
High-Speed Differential Interfaces .............................................................................................. 2–54  
Series On-Chip Termination ......................................................................................................... 2–55  
I/O Banks ........................................................................................................................................ 2–57  
MultiVolt I/O Interface ................................................................................................................. 2–60  
Chapter 3. Configuration & Testing  
IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 3–1  
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5  
Configuration ......................................................................................................................................... 3–6  
Operating Modes ................................................................................................................................... 3–6  
Configuration Schemes ......................................................................................................................... 3–7  
Cyclone II Automated Single Event Upset Detection ...................................................................... 3–7  
Custom-Built Circuitry .................................................................................................................... 3–8  
Software Interface ............................................................................................................................. 3–8  
Chapter 4. Hot Socketing, ESD & Power-On Reset  
Introduction ............................................................................................................................................ 4–1  
Cyclone II Hot-Socketing Specifications ............................................................................................ 4–1  
Devices Can Be Driven before Power-Up ..................................................................................... 4–2  
I/O Pins Remain Tri-Stated during Power-Up ............................................................................ 4–2  
Signal Pins Do Not Have Internal Current Paths to VCCIO or VCCINT Power Supplies .......... 4–2  
Hot-Socketing Feature Implementation in Cyclone II Devices ....................................................... 4–3  
ESD Protection ....................................................................................................................................... 4–5  
ESD Testing ....................................................................................................................................... 4–5  
ESD Circuitry .................................................................................................................................... 4–6  
Power-On Reset Circuitry .................................................................................................................... 4–8  
Conclusion .............................................................................................................................................. 4–9  
Chapter 5. DC Characteristics & Timing Specifications  
Operating Conditions ........................................................................................................................... 5–1  
Single-Ended I/O Standards .......................................................................................................... 5–4  
Differential I/O Standards .............................................................................................................. 5–7  
DC Characteristics for Different Pin Types ..................................................................................... 5–10  
Power Consumption ........................................................................................................................... 5–12  
Timing Specifications .......................................................................................................................... 5–13  
Preliminary & Final Timing Specifications ................................................................................. 5–14  
High Speed I/O Timing Specifications ....................................................................................... 5–16  
Chapter 6. Reference & Ordering Information  
Software .................................................................................................................................................. 6–1  
vi  
Altera Corporation  
Preliminary  

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