Contents
Contents
Device Pin-Outs ..................................................................................................................................... 6–1
Ordering Information ........................................................................................................................... 6–1
Section II. Clock Management
Revision History ..................................................................................................................... Section II–1
Chapter 7. PLLs in Cyclone II Devices
Introduction ............................................................................................................................................ 7–1
Cyclone II PLL Hardware Overview .................................................................................................. 7–2
PLL Reference Clock Generation ................................................................................................... 7–6
Software Overview ................................................................................................................................ 7–6
Clock Feedback Modes ....................................................................................................................... 7–10
Normal Mode .................................................................................................................................. 7–10
Zero Delay Buffer Mode ................................................................................................................ 7–11
No Compensation Mode ............................................................................................................... 7–12
Hardware Features .............................................................................................................................. 7–13
Clock Multiplication Division ...................................................................................................... 7–13
Programmable Duty Cycle ........................................................................................................... 7–14
Phase-Shifting Implementation .................................................................................................... 7–15
Control Signals ................................................................................................................................ 7–16
Manual Clock Switchover ............................................................................................................. 7–18
Programmable Bandwidth ................................................................................................................. 7–19
Background ..................................................................................................................................... 7–19
Implementation .............................................................................................................................. 7–22
Software Support ............................................................................................................................ 7–23
PLL Specifications ................................................................................................................................ 7–24
Clocking ................................................................................................................................................ 7–24
Global Clock Network ................................................................................................................... 7–25
Clock Control Block ....................................................................................................................... 7–28
Global Clock Network Clock Source Generation ...................................................................... 7–29
Global Clock Network Power Down ........................................................................................... 7–31
clkena signals .................................................................................................................................. 7–32
Conclusion ............................................................................................................................................ 7–33
Section III. Memory
Revision History .................................................................................................................... Section III–1
Chapter 8. Cyclone II Memory Blocks
Introduction ............................................................................................................................................ 8–1
Overview ................................................................................................................................................. 8–1
Control Signals .................................................................................................................................. 8–3
Parity Bit Support ............................................................................................................................. 8–4
Byte Enable Support ........................................................................................................................ 8–4
Altera Corporation
vii
Preliminary
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