Contents
About this Handbook .............................................................................. iii
How to Contact Altera ............................................................................................................................ iii
Typographic Conventions ...................................................................................................................... iii
Chapter Revision Dates ......................................................................... xiii
Section I. Cyclone II Device Family Data Sheet
Revision History ....................................................................................................................... Section I–2
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–1
Chapter 2. Cyclone II Architecture
Functional Description .......................................................................................................................... 2–1
Logic Elements ....................................................................................................................................... 2–3
LE Operating Modes ........................................................................................................................ 2–4
Logic Array Blocks ................................................................................................................................ 2–7
LAB Interconnects ............................................................................................................................ 2–8
LAB Control Signals ......................................................................................................................... 2–8
MultiTrack Interconnect ..................................................................................................................... 2–10
Row Interconnects .......................................................................................................................... 2–10
Column Interconnects .................................................................................................................... 2–12
Device Routing ............................................................................................................................... 2–15
Global Clock Network & Phase-Locked Loops ............................................................................... 2–16
Dedicated Clock Pins ..................................................................................................................... 2–19
Dual-Purpose Clock Pins .............................................................................................................. 2–20
Global Clock Network ................................................................................................................... 2–20
Global Clock Network Distribution ............................................................................................ 2–22
PLLs .................................................................................................................................................. 2–25
Embedded Memory ............................................................................................................................. 2–27
Memory Modes ............................................................................................................................... 2–30
Clock Modes .................................................................................................................................... 2–31
M4K Routing Interface .................................................................................................................. 2–31
Embedded Multipliers ........................................................................................................................ 2–32
Multiplier Modes ............................................................................................................................ 2–35
Embedded Multiplier Routing Interface ..................................................................................... 2–35
I/O Structure & Features .................................................................................................................... 2–37
Altera Corporation
v
Preliminary
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