Datasheet > EP20K1000CF33C7

EP20K1000CF33C7

更新时间： 2024-01-22 20:33:08

品牌	Logo	应用领域
阿尔特拉 - ALTERA		LTE 输入元件可编程逻辑
页数	文件大小	规格书
90页	524K
描述
Loadable PLD, 1.49ns, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020

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技术参数
数据手册

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EP20K1000CF33C7 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	BGA,	Reach Compliance Code：	compliant
ECCN代码：	3A001.A.7.A	HTS代码：	8542.39.00.01
风险等级：	5.61	JESD-30 代码：	S-PBGA-B1020
JESD-609代码：	e1	长度：	33 mm
专用输入次数：	4	I/O 线路数量：	708
端子数量：	1020	最高工作温度：	85 °C
最低工作温度：		组织：	4 DEDICATED INPUTS, 708 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	245
可编程逻辑类型：	LOADABLE PLD	传播延迟：	1.49 ns
认证状态：	Not Qualified	座面最大高度：	3.5 mm
最大供电电压：	1.89 V	最小供电电压：	1.71 V
标称供电电压：	1.8 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	33 mm	Base Number Matches：	1

EP20K1000CF33C7 数据手册

APEX 20KC Programmable Logic Device Data Sheet

■

Advanced interconnect structure

–

Copper interconnect for high performance

Four-level hierarchical FastTrack^®interconnect structure

providing fast, predictable interconnect delays

Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

–

Dedicated cascade chain that implements high-speed,

high-fan-in logic functions (automatically used by software tools

and megafunctions)

Interleaved local interconnect allows one LE to drive 29 other

LEs through the fast local interconnect

■

Advanced software support

–

Software design support and automatic place-and-route

provided by the Altera^®Quartus^TMII development system for

Windows-based PCs, Sun SPARCstations, and HP 9000

Series 700/800 workstations

–

Altera MegaCore^®functions and Altera Megafunction Partners

Program (AMPP^SM) megafunctions optimized for APEX 20KC

architecture available

–

NativeLink^TMintegration with popular synthesis, simulation,

and timing analysis tools

Quartus II SignalTap^®embedded logic analyzer simplifies

in-system design evaluation by giving access to internal nodes

during device operation

–

Supports popular revision-control software packages including

PVCS, RCS, and SCCS

Table 3. APEX 20KC QFP & BGA Package Options & I/O Count Notes (1), (2)

Device

208-Pin PQFP 240-Pin PQFP 356-Pin BGA 652-Pin BGA

EP20K200C

EP20K400C

EP20K600C

EP20K1000C

136

168

271

488

Altera Corporation

1 234 5 6 7...90

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