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EN25P10 PDF预览

EN25P10

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
EON 闪存
页数 文件大小 规格书
31页 386K
描述
1 Mbit Uniform Sector, Serial Flash Memory

EN25P10 数据手册

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EN25P10  
OPERATING FEATURES  
SPI Modes  
The EN25P10 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),  
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0  
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure  
3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not  
being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK  
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.  
Data output on the DO pin is clocked out on the falling edge of SCK.  
Figure 3. SPI Modes  
Page Programming  
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a  
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal  
Program cycle (of duration tPP).  
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at  
a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of  
memory.  
Sector Erase and Bulk Erase  
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the  
bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time,  
using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE)  
instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be  
preceded by a Write Enable (WREN) instruction.  
Polling During a Write, Program or Erase Cycle  
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE)  
can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress  
(WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it  
to establish when the previous Write cycle, Program cycle or Erase cycle is complete.  
Active Power, Stand-by Power and Deep Power-Down Modes  
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select  
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles  
have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power  
mode. The device consumption drops to ICC1  
.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode  
(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this  
mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID  
(RDI) instruction) is executed.  
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as  
an extra software protection mechanism, when the device is not in active use, to protect the device from  
inadvertent Write, Program or Erase instructions.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.essi.com.tw  
5
Rev. C, Issue Date: 2007/5/4  

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