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EN25P05-75GCP PDF预览

EN25P05-75GCP

更新时间: 2024-01-23 01:01:47
品牌 Logo 应用领域
晶豪 - ESMT /
页数 文件大小 规格书
30页 402K
描述
Flash Memory,

EN25P05-75GCP 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NBase Number Matches:1

EN25P05-75GCP 数据手册

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EN25P05  
SIGNAL DESCRIPTION  
Serial Data Input (DI)  
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be  
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)  
input pin.  
Serial Data Output (DO)  
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from  
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.  
Serial Clock (CLK)  
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See  
SPI Mode")  
Chip Select (CS#)  
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device  
is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the  
devices power consumption will be at standby levels unless an internal erase, program or status  
register cycle is in progress. When CS# is brought low the device will be selected, power  
consumption will increase to active levels and instructions can be written to and data read from the  
device. After power-up, CS# must transition from high to low before a new instruction will be  
accepted.  
Hold (HOLD#)  
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought  
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will  
be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same  
SPI signals.  
Write Protect (WP#)  
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in  
conjunction with the Status Register’s Block Protect (BP0, BP1) bits and Status Register Protect  
(SRP) bits, a portion or the entire memory array can be hardware protected.  
Table 1. PIN Names  
Symbol  
CLK  
DI  
Pin Name  
Serial Clock Input  
Serial Data Input  
Serial Data Output  
Chip Enable  
DO  
CS#  
WP#  
HOLD#  
Vcc  
Write Protect  
Hold Input  
Supply Voltage (2.7-3.6V)  
Ground  
Vss  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.essi.com.tw  
3
Rev. C, Issue Date: 2008/01/17  

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