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EMFA0P02V PDF预览

EMFA0P02V

更新时间: 2024-11-07 17:15:39
品牌 Logo 应用领域
杰力科技 - EXCELLIANCE /
页数 文件大小 规格书
6页 847K
描述
EDFN3X3

EMFA0P02V 数据手册

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EMFA0P02V  
P-Channel Logic Level Enhancement Mode Field Effect Transistor  
Product Summary:  
BVDSS  
-20V  
100mΩ  
-4.5A  
RDSON (MAX.)  
ID  
P-Channel MOSFET  
UIS, Rg 100% Tested  
Pb-Free Lead Plating & Halogen Free  
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)  
PARAMETERS/TEST CONDITIONS  
SYMBOL  
LIMITS  
±12  
UNIT  
Gate-Source Voltage  
VGS  
V
TA = 25 °C  
-4.5  
-3.3  
-18  
Continuous Drain Current  
ID  
TA = 70 °C  
A
Pulsed Drain Current1  
IDM  
TA = 25 °C  
2.5  
Power Dissipation  
PD  
W
°C  
TA = 70 °C  
1.6  
Operating Junction & Storage Temperature Range  
Tj, Tstg  
-55 to 150  
THERMAL RESISTANCE RATINGS  
THERMAL RESISTANCE  
SYMBOL  
RJC  
TYPICAL  
MAXIMUM  
UNIT  
Junction-to-Case  
Junction-to-Ambient3  
6
°C / W  
50  
RJA  
1Pulse width limited by maximum junction temperature.  
2Duty cycle 1%  
350°C / W when mounted on a 1 in2 pad of 2 oz copper.  
2019/6/25  
p.1  

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