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EM93LC66K PDF预览

EM93LC66K

更新时间: 2024-10-29 10:27:27
品牌 Logo 应用领域
EOREX 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 101K
描述
EEPROM

EM93LC66K 数据手册

 浏览型号EM93LC66K的Datasheet PDF文件第3页浏览型号EM93LC66K的Datasheet PDF文件第4页浏览型号EM93LC66K的Datasheet PDF文件第5页浏览型号EM93LC66K的Datasheet PDF文件第7页浏览型号EM93LC66K的Datasheet PDF文件第8页浏览型号EM93LC66K的Datasheet PDF文件第9页 
93LC46/56/57/66/86  
DEVICE OPERATION  
the DI pin on the rising edge of the clock (SK). The DO  
pin is normally in a high impedance state except when  
reading data from the device, or when checking the  
ready/busy status after a write operation.  
The 93LC46/56(57)66/86 is a 1024/2048/4096/  
16,384-bit nonvolatile memory intended for use with  
industrystandardmicroprocessors. The93LC46/56/  
57/66/86 can be organized as either registers of 16 bits  
or 8 bits. When organized as X16, seven 9-bit instruc-  
tions for 93LC46;seven 10-bit instructions for 93LC57;  
seven 11-bit instructions for 93LC56 and 93LC66;seven  
13-bitinstructionsfor93LC86;controlthereading, writing  
and erase operations of the device. When organized as  
X8, seven 10-bit instructions for 93LC46; seven 11-bit  
instructions for 93LC57; seven 12-bit instructions for  
93LC56 and 93LC66:seven 14-bit instructions for 93LC86;  
control the reading, writing and erase operations of the  
device.The93LC46/56/57/66/86operatesonasingle  
power supply and will generate on chip, the high voltage  
required during any write operation.  
The ready/busy status can be determined after the start  
ofawriteoperationbyselectingthedevice(CShigh)and  
polling the DO pin; DO low indicates that the write  
operation is not completed, while DO high indicates that  
the device is ready for the next instruction. If necessary,  
the DO pin may be placed back into a high impedance  
state during chip select by shifting a dummy 1into the  
DIpin. TheDOpinwillenterthehighimpedancestateon  
the falling edge of the clock (SK). Placing the DO pin into  
the high impedance state is recommended in applica-  
tions where the DI pin and the DO pin are to be tied  
together to form a common DI/O pin.  
Instructions, addresses, and write data are clocked into  
Figure 1. Sychronous Data Timing  
t
t
t
CSH  
SKLOW  
SKHI  
SK  
t
t
t
DIS  
DIH  
VALID  
VALID  
DI  
t
CSS  
CS  
t
t
t
CSMIN  
DIS  
PD0, PD1  
DO  
DATA VALID  
93LC46/56/57/66/86 F03  
Figure 2a. Read Instruction Timing (93LC46)  
SK  
t
CSMIN  
CS  
STANDBY  
A
A
A
0
N
N1  
DI  
1
1
0
t
HZ  
t
HIGH-Z  
HIGH-Z  
PD0  
DO  
0
D
D
D
D
0
N
N1  
1
93LC46/56/57/66/86 F04  
Doc. No. 1023, Rev. G  
6

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