Datasheet > EM6AA160TSA-4G

EM6AA160TSA-4G

更新时间： 2022-12-28 03:30:51

品牌	Logo	应用领域
钰创 - ETRON		动态存储器双倍数据速率
页数	文件大小	规格书
54页	431K
描述
16M x 16 bit DDR Synchronous DRAM (SDRAM)

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EM6AA160TSA-4G 数据手册

EtronTech

EM6AA160TSA

Addressing Mode Select Field (A3)

•

The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential

Mode and Interleave Mode support burst length of 2, 4 and 8.

Table 6. Addressing Mode

Addressing Mode

Sequential

Interleave

Burst Definition, Addressing Sequence of Sequential and Interleave Mode

•

Table 7. Burst Address ordering

Start Address

Burst Length

Sequential

Interleave

0, 1

1, 0

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

0, 1

1, 0

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

CAS Latency Field (A6~A4)

•

This field specifies the number of clock cycles from the assertion of the Read command to the first read data.

The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value

satisfying the following formula must be programmed into this field.

t_CAC(min) ≤ CAS Latency X t_CK

Table 8. CAS Latency

CAS Latency

Reserved

3 clocks

Reserved

2.5 clocks

Reserved

Etron Confidential

Rev. 1.2

May 2009

1...4 5 678 9 10...54

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