Datasheet > EM68B16CWQH-18H

EM68B16CWQH-18H

更新时间： 2022-02-26 12:34:35

品牌	Logo	应用领域
钰创 - ETRON		动态存储器双倍数据速率
页数	文件大小	规格书
60页	1029K
描述
32M x 16 bit DDRII Synchronous DRAM (SDRAM)

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数据手册

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EM68B16CWQH-18H 数据手册

EM68B16CWQH

EtronTech

Figure 35. Self refresh operation

t_CK

t_CH

t_CL

CK#

>=t_XSNR

t_RP*

>=t_XSRD

CKE

V_IH(ac)

V_IL(ac)

t_IS

t_AOFD

t_IS

V_IL(ac)

ODT

CMD

t_IS

t_IH

t_IS

t_IH

t_ISt_IH

V_IH(ac)

V_IL(ac)

V_IH(dc)

V_IL(dc)

Self

Refresh

NOP

Valid

NOTE 1 Device must be in the "All banks idle" state prior to entering Self Refresh mode.

NOTE 2 ODT must be turned off t_AOFDbefore entering Self Refresh mode, and can be

turned on again when t_XSRDtiming is satisfied.

NOTE 3 t_XSRDis applied for Read or a Read with autoprecharge command.

_XSNRis applied for any command except a Read or a Read with autoprecharge command.

Figure 36. Basic power down entry and exit timing diagram

CK#

t_IH

t_IS

t_ISt_IH

t_IH

t_IS

t_IH

CKE

VALID

or NOP

VALID

NOP

VALID

Command

t_{CKE min}

t_XP,t_XARD

t_CKE(min)

t_XARDS

Exit Power-Down mode

Enter Power-Down mode

Don't Care

Figure 37.1.CKE intensive environment

CK#

t_CKE

CKE

t_CKE

NOTE: DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation

Rev. 1.6

Oct. /2015

1...52 53 545556 57 58...60

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