Datasheet > EM63A165TS-6G

EM63A165TS-6G

更新时间： 2024-01-26 06:56:48

品牌	Logo	应用领域
钰创 - ETRON		内存集成电路光电二极管动态存储器
页数	文件大小	规格书
73页	1390K
描述
16Mega x 16 Synchronous DRAM (SDRAM)

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技术参数
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EM63A165TS-6G 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
包装说明：	TSOP2,	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.24
风险等级：	5.66	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	5 ns	其他特性：	AUTO/SELF REFRESH
JESD-30 代码：	R-PDSO-G54	长度：	22.22 mm
内存密度：	268435456 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	54
字数：	16777216 words	字数代码：	16000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	16MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP2
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.2 mm
自我刷新：	YES	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10.16 mm
Base Number Matches：	1

EM63A165TS-6G 数据手册

EtronTech

EM63A165

Commands

BankActivate

(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A12 = Row Address)

The BankActivate command activates the idle bank designated by the BA0,1 signals. By

latching the row address on A0 to A12 at the time of this command, the selected row access is

initiated. The read or write operation in the same bank can occur after a time delay of t_RCD(min.) from

the time of bank activation. A subsequent BankActivate command to a different row in the same bank

can only be issued after the previous active row has been precharged (refer to the following figure).

The minimum time interval between successive BankActivate commands to the same bank is defined

by t_RC(min.). The SDRAM has four internal banks on the same chip and shares part of the internal

circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks.

t_RRD(min.) specifies the minimum time required between activating different banks. After this

command is used, the Write command and the Block Write command perform the no mask write

operation.

Tn+3

Tn+4

Tn+5

Tn+6

CLK

..............

Bank A

Row Addr.

Bank A

Col Addr.

Bank B

Row Addr.

Bank A

Row Addr.

ADDRESS

RAS# - RAS# delay time (tRRD)

NOP

RAS# - CAS# delay (tRCD)

NOP

R/W A with

AutoPrecharge

Bank A

Activate

Bank B

Activate

Bank A

Activate

..............

COMMAND

NOP

RAS# Cycle time (tRC

)

AutoPrecharge

Begin

: "H" or "L"

BankActivate Command Cycle

(Burst Length = n, CAS# Latency = 3)

BankPrecharge command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9, A11 and A12 = Don't care)

The BankPrecharge command precharges the bank disignated by BA signal. The precharged

bank is switched from the active state to the idle state. This command can be asserted anytime after

t_RAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any

bank can be active is specified by t_RAS(max.). Therefore, the precharge function must be performed in

any active bank within t_RAS(max.). At the end of precharge, the precharged bank is still in the idle state

and is ready to be activated again.

PrechargeAll command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9, A11 and A12 = Don't care)

The PrechargeAll command precharges all banks simultaneously and can be issued even if all

banks are not in the active state. All banks are then switched to the idle state.

Read command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address)

The Read command is used to read a burst of data on consecutive clock cycles from an active

row in an active bank. The bank must be active for at least t_RCD(min.) before the Read command is

issued. During read bursts, the valid data-out element from the starting column address will be

available following the CAS# latency after the issue of the Read command. Each subsequent data-out

element will be valid by the next positive clock edge (refer to the following figure). The DQs go into

high-impedance at the end of the burst unless other command is initiated. The burst length, burst

sequence, and CAS# latency are determined by the mode register, which is already programmed. A

full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and

continue).

Rev 1.1 Apr. 2007

1...3 4 567 8 9...73

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与EM63A165TS-6G相关器件

型号	品牌	描述	获取价格	数据表
EM63A165TS-6IG	ETRON	16M x 16 bit Synchronous DRAM (SDRAM)	获取价格
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EM63A165TS-7IG	ETRON	16M x 16 bit Synchronous DRAM (SDRAM)	获取价格
EM63B165TS-5ISG	ETRON	32M x 16 bit Synchronous DRAM (SDRAM)	获取价格
EM63B165TS-5SG	ETRON	32M x 16 bit Synchronous DRAM (SDRAM)	获取价格
EM63B165TS-6ISG	ETRON	32M x 16 bit Synchronous DRAM (SDRAM)	获取价格

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