5秒后页面跳转
捷配首页

Datasheet > EM63A165TS-6G
EM63A165TS-6G PDF预览

EM63A165TS-6G

更新时间： 2024-02-09 03:17:08
品牌 Logo 应用领域
钰创 - ETRON 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
73页 1390K
描述
16Mega x 16 Synchronous DRAM (SDRAM)

阅读下载

获取价格

EM63A165TS-6G 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：TSOP2,Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.24
风险等级：5.66访问模式：FOUR BANK PAGE BURST
最长访问时间：5 ns其他特性：AUTO/SELF REFRESH
JESD-30 代码：R-PDSO-G54长度：22.22 mm
内存密度：268435456 bit内存集成电路类型：SYNCHRONOUS DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：54
字数：16777216 words字数代码：16000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：16MX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.2 mm
自我刷新：YES最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10.16 mm
Base Number Matches：1

EM63A165TS-6G 数据手册

 浏览型号EM63A165TS-6G的Datasheet PDF文件第1页浏览型号EM63A165TS-6G的Datasheet PDF文件第2页浏览型号EM63A165TS-6G的Datasheet PDF文件第4页浏览型号EM63A165TS-6G的Datasheet PDF文件第5页浏览型号EM63A165TS-6G的Datasheet PDF文件第6页浏览型号EM63A165TS-6G的Datasheet PDF文件第7页 
EtronTech  
EM63A165  
Pin Descriptions  
Table 1. Pin Details of EM63A165  
Description  
Symbol  
Type  
CLK  
Input  
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled  
on the positive edge of CLK. CLK also increments the internal burst counter and  
controls the output registers.  
CKE  
Input  
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If  
CKE goes low synchronously with clock(set-up and hold time same as other  
inputs), the internal clock is suspended from the next clock cycle and the state of  
output and burst address is frozen as long as the CKE remains low. When all  
banks are in the idle state, deactivating the clock controls the entry to the Power  
Down and Self Refresh modes. CKE is synchronous except after the device  
enters Power Down and Self Refresh modes, where CKE becomes  
asynchronous until exiting the same mode. The input buffers, including CLK, are  
disabled during Power Down and Self Refresh modes, providing low standby  
power.  
BA0,BA1  
Input  
Bank Select: BA0,BA1 input select the bank for operation.  
BA1  
0
BA0  
0
Select Bank  
BANK #A  
BANK #B  
BANK #C  
BANK #D  
0
1
1
0
1
1
A0-A12  
Input  
Address Inputs: A0-A11 are sampled during the BankActivate command (row  
address A0-A11) and Read/Write command (column address A0-A8 with A10  
defining Auto Precharge) to select one location out of the 4M available in the  
respective bank. During a Precharge command, A10 is sampled to determine if  
all banks are to be precharged (A10 = HIGH). The address inputs also provide  
the op-code during a Mode Register Set command.  
CS#  
Input  
Input  
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the  
command decoder. All commands are masked when CS# is sampled HIGH. CS#  
provides for external bank selection on systems with multiple banks. It is  
considered part of the command code.  
RAS#  
Row Address Strobe: The RAS# signal defines the operation commands in  
conjunction with the CAS# and WE# signals and is latched at the positive edges  
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted  
"HIGH," either the BankActivate command or the Precharge command is  
selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate  
command is selected and the bank designated by BS is turned on to the active  
state. When the WE# is asserted "LOW," the Precharge command is selected  
and the bank designated by BS is switched to the idle state after the precharge  
operation.  
CAS#  
Input  
Column Address Strobe: The CAS# signal defines the operation commands in  
conjunction with the RAS# and WE# signals and is latched at the positive edges  
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column  
access is started by asserting CAS# "LOW." Then, the Read or Write command  
is selected by asserting WE# "LOW" or "HIGH."  
3
Rev 1.1 Apr. 2007  
1234567...73

下载PDF

与EM63A165TS-6G相关器件

型号 品牌 描述 获取价格 数据表
EM63A165TS-6IG ETRON 16M x 16 bit Synchronous DRAM (SDRAM)

获取价格
EM63A165TS-7G ETRON 16Mega x 16 Synchronous DRAM (SDRAM)

获取价格
EM63A165TS-7IG ETRON 16M x 16 bit Synchronous DRAM (SDRAM)

获取价格
EM63B165TS-5ISG ETRON 32M x 16 bit Synchronous DRAM (SDRAM)

获取价格
EM63B165TS-5SG ETRON 32M x 16 bit Synchronous DRAM (SDRAM)

获取价格
EM63B165TS-6ISG ETRON 32M x 16 bit Synchronous DRAM (SDRAM)

获取价格

与EM63A165TS-6G相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证