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EH3700TS-42.901M PDF预览

EH3700TS-42.901M

更新时间: 2024-11-12 06:51:23
品牌 Logo 应用领域
日蚀 - ECLIPTEK 石英晶振
页数 文件大小 规格书
10页 795K
描述
CMOS, Quartz Crystal Clock Oscillators XO (SPXO) LVCMOS (CMOS) 2.5Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) Quartz Crystal Clock Oscillators XO (SPXO) LVCMOS (CMOS) 2.5Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)

EH3700TS-42.901M 数据手册

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Ecliptek | EH37 Series Oscillator  
http://www.ecliptek.com/oscillators/EH37/  
Log On | 714-433-1200 | Email Customer Support  
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EH37 Series Oscillator  
Quartz Crystal Clock Oscillators XO (SPXO) LVCMOS (CMOS) 2.5Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)  
2011/65 +  
168 SVHC  
2015/863  
Revision E 03/12/2015  
ectrical Specifications  
Nominal Frequency  
1.000MHz to 200.000MHz  
Some frequencies within this range may not be available.  
requency  
(Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the  
olerance/Stability  
Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year  
Aging at 25°C, Shock, and Vibration)  
±100ppm Maximum  
±50ppm Maximum  
±25ppm Maximum  
±20ppm Maximum  
Operating Temperature  
ange  
0°C to +70°C  
-40°C to +85°C  
ging at 25°C  
upply Voltage  
±5ppm/year Maximum  
2.5V  
±5%  
DC  
nput Current (No  
oad)  
6mA Maximum over Nominal Frequency of 1.000MHz to 25.000MHz  
7mA Maximum over Nominal Frequency of 25.000001MHz to 75.000MHz  
8mA Maximum over Nominal Frequency of 75.000001MHz to 100.000MHz  
9mA Maximum over Nominal Frequency of 100.000001MHz to 200.000MHz  
Output Voltage Logic  
I
= -8mA  
OH  
High (V  
)
90% of V  
Minimum  
Maximum  
OH  
DD  
Output Voltage Logic  
ow (V  
I
= +8mA  
OL  
10% of V  
)
OL  
DD  
uty Cycle  
Measured at 50% of Waveform  
50 ±10(%)  
50 ±5(%)  
ise Time/Fall Time  
Measured at 20% to 80% of Waveform  
6nSec Maximum from 1.000MHz to 50.000MHz  
4nSec Maximum from 50.000001MHz to 75.000MHz  
2nSec Maximum from 75.000001MHz to 200.000MHz  
oad Drive Capability  
Output Logic Type  
in 1 Connection  
15pF Maximum  
CMOS  
Tri-State (High Impedance)  
ri-State Input Voltage  
90% of V  
10% of V  
Minimum or No Connection to Enable Output  
Maximum to Disable Output (High Impedance)  
DD  
DD  
tandby Current  
MS Phase Jitter  
10µA Maximum (Pin 1 = Ground)  
Fj=12kHz to 20MHz  
20pSec Typical, 30pSec Maximum  
eriod Jitter (RMS)  
13pSec Typical  
1 of 10  
28-Jan-2016 1:06 PM  

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