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EH3500ETTS-6.000M TR PDF预览

EH3500ETTS-6.000M TR

更新时间： 2024-11-09 15:31:35
品牌 Logo 应用领域
日蚀 - ECLIPTEK 石英晶振
页数 文件大小 规格书
6页 164K
描述
CMOS, Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD)

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EH3500ETTS-6.000M TR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SMD 3.2mm x 5.0mm
针数：4Reach Compliance Code：163
风险等级：5.65老化：5 PPM/YEAR
技术：CMOSBase Number Matches：1

EH3500ETTS-6.000M TR 数据手册

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RoHS  
Pb  
EH3500ETTS-6.000M  
EH35 00 ET  
TS -6.000M  
Series  
Nominal Frequency  
6.000MHz  
RoHS Compliant (Pb-free) 5.0V 4 Pad 3.2mm x 5mm  
Ceramic SMD HCMOS/TTL High Frequency Oscillator  
Pin 1 Connection  
Tri-State (Disabled Output: High Impedance)  
Frequency Tolerance/Stability  
±100ppm Maximum  
Duty Cycle  
50 ±10(%)  
Operating Temperature Range  
-40°C to +85°C  
ELECTRICAL SPECIFICATIONS  
Nominal Frequency  
6.000MHz  
Frequency Tolerance/Stability  
±100ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the  
Operating Temperature Range, Supply Voltage Change, Output Load Change, 1st Year Aging at 25°C,  
Shock, and Vibration)  
Aging at 25°C  
±5ppm/year Maximum  
Operating Temperature Range  
Supply Voltage  
-40°C to +85°C  
5.0Vdc ±10%  
Input Current  
50mA Maximum (No Load)  
Output Voltage Logic High (Voh)  
Output Voltage Logic Low (Vol)  
Rise/Fall Time  
2.4Vdc Minimum with TTL Load, Vdd-0.4Vdc Minimum with HCMOS Load (IOH = -16mA)  
0.4Vdc Maximum with TTL Load, 0.5Vdc Maximum with HCMOS Load (IOL = +16mA)  
6nSec Maximum (Measured at 0.8Vdc to 2.0Vdc with TTL Load or at 20% to 80% of waveform with  
HCMOS Load)  
Duty Cycle  
50 ±10(%) (Measured at 1.4Vdc with TTL Load or at 50% of waveform with HCMOS Load)  
10TTL Load or 50pF HCMOS Load Maximum  
CMOS  
Load Drive Capability  
Output Logic Type  
Pin 1 Connection  
Tri-State (Disabled Output: High Impedance)  
Tri-State Input Voltage (Vih and Vil)  
+2.2Vdc Minimum to enable output, +0.8Vdc Maximum to disable output (High Impedance), No Connect to  
enable output.  
Absolute Clock Jitter  
±250pSec Maximum, ±100pSec Typical  
±50pSec Maximum, ±30pSec Typical  
10mSec Maximum  
One Sigma Clock Period Jitter  
Start Up Time  
Storage Temperature Range  
-55°C to +125°C  
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS  
Fine Leak Test  
MIL-STD-883, Method 1014, Condition A  
MIL-STD-883, Method 1014, Condition C  
MIL-STD-202, Method 213, Condition C  
MIL-STD-202, Method 210  
Gross Leak Test  
Mechanical Shock  
Resistance to Soldering Heat  
Resistance to Solvents  
Solderability  
MIL-STD-202, Method 215  
MIL-STD-883, Method 2003  
Temperature Cycling  
Vibration  
MIL-STD-883, MEthod 1010  
MIL-STD-883, Method 2007, Condition A  
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/17/2010 | Page 1 of 6  
123456

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