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EFR32BG21B010F1024IM32 PDF预览

EFR32BG21B010F1024IM32

更新时间: 2023-12-06 20:00:54
品牌 Logo 应用领域
芯科 - SILICON 无线
页数 文件大小 规格书
83页 1425K
描述
EFR32BG21B010F1024IM32 EFR32BG21 系列 2 无线 SoC 包含 80 MHz ARM Cortex-M33 内核,可提供卓越的处理能力,而集成的安全子系统可提供领先

EFR32BG21B010F1024IM32 数据手册

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EFR32BG21B Gecko Wireless SoC Family Data Sheet  
System Overview  
3.5.3 Real Time Clock with Capture (RTCC)  
The Real Time Clock with Capture (RTCC) is a 32-bit counter providing timekeeping down to EM3. The RTCC can be clocked by any of  
the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals.  
A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-  
cation software.  
3.5.4 Back-Up Real Time Counter (BURTC)  
The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC  
can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined inver-  
vals.  
3.5.5 Watchdog Timer (WDOG)  
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed  
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can  
also monitor autonomous systems driven by the Peripheral Reflex System (PRS).  
3.6 Communications and Other Digital Peripherals  
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)  
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous  
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-  
porting:  
• ISO7816 SmartCards  
• IrDA  
I2S  
3.6.2 Inter-Integrated Circuit Interface (I2C)  
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and  
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10  
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The  
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-  
fers. Automatic recognition of slave addresses is provided in active and low energy modes. Note that not all instances of I2C are avalia-  
ble in all energy modes.  
3.6.3 Peripheral Reflex System (PRS)  
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.  
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-  
erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)  
can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving pow-  
er.  
3.7 Secure Vault High Features  
A dedicated Hardware Secure Engine containing its own CPU enables the Secure Vault High functions. It isolates cryptographic func-  
tions and data from the host Cortex-M33 core and provides the following security features:  
• Secure Boot with Root of Trust and Secure Loader (RTSL)  
• Cryptographic Accelerator  
• True Random Number Generator (TRNG)  
• Secure Debug with Lock/Unlock  
• DPA Countermeasures  
• Secure Key Management with PUF  
• Anti-Tamper  
• Secure Attestation  
silabs.com | Building a more connected world.  
Rev. 1.0 | 10  

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