Datasheet > EDS1216CABH

EDS1216CABH

更新时间： 2025-08-11 22:30:43

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器
页数	文件大小	规格书
49页	694K
描述
128M bits SDRAM (8M words x 16 bits)

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EDS1216CABH 数据手册

DATA SHEET

128M bits SDRAM

EDS1216AABH, EDS1216CABH

(8M words × 16 bits)

Pin Configurations

Description

The EDS1216AABH, EDS1216CABH are 128M bits

SDRAM organized as 2,097,152 words × 16 bits × 4

banks. All inputs and outputs are synchronized with

the positive edge of the clock.

/xxx indicate active low signal.

54-ball FBGA

Supply voltages are 3.3V (EDS1216AABH) and 2.5V

(EDS1216CABH).

VSS DQ15 VSSQ

DQ14 DQ13 VDDQ

DQ12 DQ11 VSSQ

DQ10 DQ9 VDDQ

VDDQ DQ0

VSSQ DQ2

VDDQ DQ4

VSSQ DQ6

VDD

DQ1

DQ3

DQ5

They are packaged in 54-ball FBGA.

Features

• 3.3V and 2.5V power supply

• Clock frequency: 133MHz (max.)

• Single pulsed /RAS

• ×16 organization

DQ8

VSS

CKE

VDD LDQM DQ7

/CAS /RAS /WE

• 4 banks can operate simultaneously and

independently

UDQM CLK

• Burst read/write operation and burst read/single

write operation capability

A11

BA0

BA1

/CS

A10

VDD

• Programmable burst length (BL): 1, 2, 4, 8, full page

• 2 variations of burst sequence

Sequential (BL = 1, 2, 4, 8, full page)

Interleave (BL = 1, 2, 4, 8)

VSS

• Programmable /CAS latency (CL): 2, 3

• Byte control by UDQM and LDQM

• Refresh cycles: 4096 refresh cycles/64ms

• 2 variations of refresh

(Top view)

A0 to A11

BA0, BA1

Address inputs

Bank select

DQ0 to DQ15

CLK

Data inputs/ outputs

Clock input

Auto refresh

Self refresh

CKE

Clock enable

• FBGA package with lead free solder (Sn-Ag-Cu)

/CS

Chip select

/RAS

Row address strobe

Column address strobe

Write enable

/CAS

/WE

LDQM /UDQM Input/output mask

VDD

VSS

Power supply

Ground

VDDQ

VSSQ

Power supply for DQ

Ground for DQ

No connection

Document No. E0410E40 (Ver. 4.0)

Date Published February 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2003-2005

12 3 4 5 6 7...49

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